Efficient Circuit Design of Reversible Square

Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.

Reversible logic is widely used in optical information processing, bioinformatics and quantum computing etc. Reversible logic requires ancilla inputs and garbage outputs to keep reversibility. However, it needs to reduce the number of these logic bits in complex designs, such as reversible quantum multipliers. In the existing literatures, researchers have optimized the multi-operand addition part and the partial product generation part of reversible quantum multipliers separately, which produce considerable overhead in terms of garbage outputs and ancilla inputs. This paper presents a novel method to reduce garbage outputs and ancilla inputs of reversible quantum multipliers. The proposed methodology converts some garbage outputs of the previous calculation to zeros, which are then served as ancilla inputs of the later calculation. In order to verify the proposed method, we apply it to two typical reversible quantum multiplier designs. Results show that the proposed method can greatly reduce the number of garbage outputs and ancilla inputs compared to the existing designs.

Over the last decades, designing reversible arithmetic circuits is one of the interesting research areas because of its ability to reduce power consumption in the circuits. This paper proposes two new design approaches of reversible binary-coded decimal (BCD) multiplier. The realization of such BCD multiplier has been achieved through binary multipliers, multiplexers, and a binary-to-BCD converter. Four types of multiplications, viz. [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text] multiplications, have been utilized for such binary multiplication and are implemented parallelly as a combined multiplier to reduce ancilla inputs (AIs) and garbage outputs (GOs). We also propose a novel reversible BCD adder for a reversible binary-to-BCD converter with reducing AIs and GOs. The first design of the reversible BCD multiplier is integrated with the proposed BCD adder in the binary-to-BCD converter. Furthermore, the proposed reversible BCD adder is modified to reduce the AIs and the GOs, which is then integrated into the second design of the reversible BCD multiplier. The results offer appreciable reductions of AIs and GOs by at least [Formula: see text]16% and [Formula: see text]43%, respectively, compared to the existing designs found in the literature.

Reversible computing is one of the most promising technologies in the design of low‐power digital circuits, optical information processing, quantum computing, DNA computing, digital signal processing, and nanotechnology. The main purpose of the design of reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. A gate/block is reversible if the number of inputs and the number of outputs are equal and there is one‐to‐one correspondence between them. Latches are considered as one of the most important digital structures that are widely used as building blocks in the design of sequential circuits. Here, eight new reversible blocks are first offered. Then using some of them, several effective designs of reversible D, T, and J‐K latches are proposed. The results of the evaluations indicate that the proposed latches are superior in terms of quantum cost (QC) than previous designs. Moreover, they are very close to or better than the best previous designs in terms of criteria such as gate count (GC), constant inputs (CI), and garbage outputs (GO).

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

Power dissipation has become the major concern for circuit design and implementation. Reversible Logic is the best alternative to Irreversible Logic in terms of low power consumption. Circuits designed using reversible logic have a wide array of applications. The Quantum Cost, Garbage Outputs, Ancillary Inputs and Delay are some of the parameters of reversible circuits that can be used to determine their efficiency and compare them with existing works. Optimization of these parameters are highly essential. Garbage Outputs is an important parameter that must be considered. This paper presents a design for a Reversible Radix-4 Booth Multiplier that is optimized in Garbage Cost and Ancillary inputs. The design proposed is capable of both signed and unsigned multiplication. The optimization in Garbage Cost ensures lower heat dissipation. The Encoded Booth Algorithm or Radix-4 Booth Algorithm reduces the number of partial products generated in signed multiplication to half the number generated using a Radix-2 signed multiplier making it suitable for Digital Signal Processors. The design proposed is compared to existing multiplier circuits and the parameters are tabulated.

Reversible logic has gained importance in the last few decades because of its low power dissipation. Quantum cost, garbage outputs, ancillary inputs and gate count are some of the performance parameters used to weigh reversible designs against one another. Optimization of these parameters is of great relevance to obtain an optimal design. This paper presents the design of a reversible squaring and sum-of-squares units explored for a trade-off between garbage outputs and quantum cost. The proposed work focuses on the design of dedicated unsigned and signed squaring units with a generalized methodology for n-bit squaring unit and novel sum-of-squares unit. For the optimization of the squaring circuit, the redundant product terms from the multiplier logic are eliminated. The ancillary inputs are regenerated due to which the extraneous garbage outputs are reduced. The obtained results are compared with existing state-of-art designs for performance. The garbage-cost optimized designs were found to have a 50% improvement of both ancillary inputs and garbage outputs over the direct implementation; 51% improvement of ancillary inputs and 27% improvement of quantum cost over the garbage free designs. Usage of optimized dedicated sum-of-squares unit enhances the functionality of the digital signal processor.

Over the last few decades, research in reversible logic has increasingly become very popular and it is gaining greater momentum in the present word. Reversible logic has started finding concert applications in quantum computing, optical computing, nano-technology based system, low-power CMOS design, VLSI design. The principal objective of this work is to argue for quantum implementation of various reversible logic gates by using C-NOT, Controlled-V and Controlled-V+ gates. The present work presents Binary coded decimal adder (BCD) in terms of number of gates, garbage outputs, quantum cost, delay and hardware complexity compared to existing design.

In today’s electrical or electronic designing, power dissipation becomes dominant. The promising alternative to these technologies is the reversible computing. Because for irreversible circuits, information is lost and it dissipates energy as heat. The dissipated energy is proportional to the number of bits lost during computation. In case of reversible circuits, they do not dissipate energy in a large amount as irreversible circuits. So information is not lost in reversible circuits during the execution of operation. Thus generation of unique outputs from the particular inputs and reconstruction of inputs from the particular outputs can be achievable. So in the view point of designing issues, reversible logic is a promising field of research that finds applications in low power computing, quantum computing, optical computing and other emerging computing technologies, bioinformatics and nanotechnology-based systems. Here, an approach for the designing of optimized reversible parallel multiplier (ORPM) by reversible gates has been followed. In this regard, this paper represents a new partial reversible gate RPPG for partial product generation for the designing of ORPM. Also, two designing methods are proposed to design ORPM and a comparison is also made between these two methods and the existing reversible multiplier circuits reported in the literature in perspective of the number of reversible gates, constant input, garbage output and total logical calculation.KeywordsReversible logicReversible gateReversible parallel multiplierGarbage outputConstant inputs

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts. Keywords: Reversible Logic, Parity Preserving Reversible Gate, IG Gate, FTFA and Carry Skip Logic. doi: 10.3329/jbas.v32i2.2431 Journal of Bangladesh Academy of Sciences Vol.32(2) 2008 234-250

Reversible logic preserves information and provides low power computing. Floating point multiplier is an important part of arithmetic in DSP applications. IEEE754 provide two basic and widely used formats for representing floating point numbers namely Single Precision Floating point (SPFP) and Double Precision Floating Point (DPFP). In this paper, we have proposed designs for Reversible SPFP and DPFP point multiplier which requires optimum design of 24X24 and 53X53 multiplying circuitry with reversible gates respectively. Also we presented sign bit calculation and exponent bit calculation circuits by reversible logic. Reversible Mantissa bits calculation circuitry requires consumes more area as it has large value of quantum cost and garbage outputs as compare to reversible sign bit and exponent bits calculation circuitry. So, we mainly focused our work on to minimize the area consumed by the reversible mantissa bits calculation circuit by minimizing the value of quantum cost and garbage outputs of it. In this paper, we presented two ways for partial products generation with reversible gates. We propose a new design of reversible 12X12 reversible Wallace tree multiplier for single precision and double precision mantissa multiplier circuit. Also 5X5 and 5X12 reversible Wallace tree multiplier for double precision multiplier. Here we use the optimized designs of reversible half adder, Full adder and 4:2 compressors. In the final summation stage, we carefully shifted the product terms and add them. For this stage we have carefully chosen the adders and compressor in such way to get the optimized results in terms of quantum cost and Garbage output. We have also shown the improvement in single precision floating point multiplier in terms of Quantum cost and Garbage output.

In modern Very-Large-Scale Integration (VLSI) systems, minimizing energy dissipation and information loss is a major challenge. Conventional logic gates suffer from irreversibility, leading to reduced efficiency in advanced computing applications. Reversible logic provides a promising solution by ensuring bijective input-output mapping, preserving information, and reducing heat generation. This paper presents the design of hybrid adder circuits—including ripple carry, carry skip, carry save, and carry select adders—using reversible logic gates such as Feynman, Fredkin, Peres, and HNG gates. The proposed designs focus on reducing quantum cost, garbage outputs, and ancillary inputs compared to conventional approaches. Simulation and synthesis were performed using Xilinx Vivado and ISE tools. Results demonstrate significant improvements, achieving a quantum cost as low as 28 for ripple carry and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{4 5}$</tex> for carry skip adder, while reducing the Total Reversible Logic Implementation Cost (TRLIC). These findings highlight the potential of reversible logic-based adders in low-power, high-performance VLSI and emerging quantum computing applications.

An improved KFDD based reversible circuit synthesis method

Reversible logic is an emerging research area. Its ability to reduce the power dissipation has made these circuits lossless circuits. Irreversible circuits or classical circuits have energy dissipation is proportional to the number of bits lost during computation. The reversible circuits do not lose information and can generate unique outputs from specified inputs and vice versa. It has application in diverse fields such as low power CMOS design, optical information processing, cryptography, quantum computation and nanotechnology. This paper proposes a reversible design of Flip Flops, Counters and Universal shift register. Universal shift register is an important memory element of the sequential circuit family. In this paper we proposed efficient design of reversible universal shift register that is optimized in terms of quantum cost, delay, garbage outputs. Each module has been coded using Verilog then simulated using Modelsim and prototyped in Xilinx-Spartan 3.

Reversible logic has become very promising for low-power design using emerging computing technologies. A number of good works have been reported on reversible combinational circuit design. However, only a few works reported on the design of reversible latches and flip-flops on the top of reversible combinational gates and suggested that sequential circuits be built by replacing the latches and flip-flops and associated combinational gates of the traditional irreversible designs by their reversible counter parts. This replacement technique is not very promising, because it leads to high quantum cost and garbage outputs. In this paper, we propose a novel approach of designing synchronous sequential circuits directly from reversible gates using pseudo Reed-Muller expressions representing the state transition and the output functions of the circuit. We present designs of arbitrary synchronous sequential circuit as well as practically important sequential circuits such as counters and registers. It is found that our direct designs save 1.54%-49.09% quantum cost and 51.43%-81.82% garbage outputs than the replacement design approach suggested earlier.