Design, study, modeling and control of a modified Sheppard-Taylor PFC

The inherent dead angles of the input line current in buck power factor correction (PFC) converter deteriorates the power factor (PF). This article introduces a new bridgeless single-phase buck (PFC) converter with reduced components. This converter is designed to operate in discontinuous conduction mode (DCM) to achieve inherent PFC with a simple structure. The DCM operation gives additional advantages, such as low turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> losses and reduced complexity of the control circuitry. Unlike the buck PFCs, in which dead angle is the main drawback, in the proposed converter the PF is improved and the dead angle is eliminated by applying an auxiliary switch. Besides, the efficiency is further improved by employing the bridgeless structure. The switching losses are eliminated due to achieved zero current switching (ZCS) at the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> of the main switches, and also ZCS at the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and zero voltage switching at turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> of the auxiliary switch. The proposed topology is successfully implemented on a 120 W prototype converter at 110 Vrms input voltage and 48 V output voltages, and its performance is experimentally verified. The results show the total harmonic distortion of 5.3% and efficiency of 93.1% at the rated load.

In this paper, a series-capacitor-based interleaving buck power factor correction (PFC) converter is proposed, the intermediate energy storage capacitance of which is operated at discontinuous capacitor voltage mode (DCVM), and automatic power factor (PF) correction for this converter is obtained. Moreover, the voltage across the series capacitor of the proposed PFC converter is clamped at the input voltage, and thus peak voltage stress existed in the traditional DCVM buck PFC could be relieved. By effectively regulating the charge/discharge time for the series capacitor, ultrahigh step-down conversion ratio of the proposed converter is achieved, the conversion ratio of which is independent of the duty cycle and only related to the switching frequency and circuit parameters. Therefore, high PF can be obtained due to very narrow deadtime of the input current. Meanwhile, the proposed PFC converter can realize the soft turn- on of part power switch and soft turn- off of part power diodes. In addition, comparing with the traditional discontinuous inductor current mode PFC, the input current of the proposed PFC converter is continuous so that the peak value and root-mean-square value of input current can be reduced. The operational principle, performance analysis, and parameter design principle are given in this paper. The analysis results show that the PF and total harmonic distortion are also independent of the duty cycle. Finally, a 220-Vac input, 60 W/15 V output experimental prototype is built to verify the validity of the theoretical analysis.

In the last decade, the amount of electronic equipment connected to the AC line has been increased; this equipment presents low values of power factor (PF) and high total harmonic distortion (THD) due to their nonlinear behavior. The personal computer (PC) is one piece of electronic equipment that has these problems, the main reason being because it was decided to develop a switching mode power supply (SMPS), for the PC, with power factor correction (PFC). In this paper, the experimental results of the SMPS prototype for PC applications, which includes a PFC feature, are presented. Analysis of the design compromises that must be kept in mind in order to develop a SMPS with PFC has been included. This analysis evaluates the compromises that must be considered when in the design of a SMPS with PFC, we try to obtain the best power factor (PF), total harmonic distortion (THD) and construction cost.

This paper focuses on the control design of a differential boost inverter when used in single-stage grid-tied PV systems. The inverter performs both Maximum Power Point Tracking (MPPT) at the DC side and Power Factor Correction at the AC side. At first, the state-space time-domain averaged model of the inverter is derived and the small signal frequency domain model is obtained using a quasi-static approximation in which the inverter is treated as a DC–DC converter with a slowly varying output voltage. Then, the controllers are designed using a three-loop strategy in which the inverter inductor currents loop is used for suitable compensation, the DC Photovoltaic (PV) voltage loop is used for MPPT and the output grid current loop is used for Power Factor Correction (PFC) and active power control. The selection of the control parameters is based on a compromise among suitable system performances such as settling time of the input PV voltage, the sampling period of the MPPT, total harmonic distortion of the output grid current, power factor as well as suppression of subharmonic oscillation for all the range of the operating duty cycle. The resulting design ensures that the oscillations of the voltage, current and power at the DC side and the grid current at the AC side are effectively controlled. The validity of the proposed control design is verified by numerical simulations performed on the switched model of the system demonstrating its robustness and fast response under irradiance variations and MPPT perturbations despite the nonlinearity and complexity of the system.

Power factor correction (PFC) is widely used in ac–dc converters to improve power quality. The current-source charge pump (CS-CP) PFC converter has the advantages of simple structure, easy control, and low cost, but it can only obtain a high power factor (PF) over a narrow input range. The operation principle of the CS-CP PFC converter and the input voltage range are analyzed in this article. In order to obtain a high PF over a wide input voltage range, in this article, a variable turn ratio CS-CP PFC converter is proposed. By adjusting the turn ratio according to the variation of the input voltage, the proposed converter can obtain a high PF over a wide input voltage range, reduce the voltage stress of the bus capacitor, and solve the problem of insufficient voltage gain at low input voltage. The operating modes and the wide input voltage range of the proposed converter are analyzed, and the relevant parameters are given. A 40-W experimental prototype operating with the input voltage range of 100–242 Vac is built to verify the theoretical analysis. The proposed converter obtains the PF of 0.946–0.991 and its total harmonic distortion of current can satisfy the IEC 61000-3-2-2020 Class-C Standard in the whole input voltage.

In this paper, a comparison of three high power single-phase power factor correction (PFC) pre-regulators is proposed. The topologies discussed are the boost converter, the interleaved boost converter and the dual boost converter. The control system used to perform the PFC is based in predictive current control laws and an algorithm to detect the conduction modes is also used, once the converters operate in mixed conduction mode. All topologies have the same input current, input voltage, output voltage, load and controller. Furthermore, all topologies have the same rms current and total harmonic distortion (THD) values of the input current, and, therefore, equal input filters. The comparison parameters are: input power factor, conducted electromagnetic interference (EMI), core losses, power losses, heat-sink volume, total volume, efficiency and number of components and devices. Theoretical and experimental results are presented to analyze the comparisons between the converters.

This paper proposes a new energy management method using the internal capacitor for energy buffer in the boost cascaded buck-boost (BoCBB) power factor correction (PFC) converter. The theory and existing shortcoming of the conventional PFC are first analyzed. A new energy management method realized by model predictive control (MPC) is proposed to maximize the benefit of the internal capacitor with a considerably reduced capacitance. A 500W PFC is used as a case study. It is found that the energy management method offers more effective control of the output voltage and input current with a much-reduced capacitance. Experimental results validate the proposed concept on a GaN FET based BoCBB PFC prototype.

In this paper, a new bridgeless single phase ac-dc power factor correction (PFC) rectifiers based on Buck topology operating in Discontinuous Capacitor Voltage Mode (DCVM) is proposed. The bridgeless topology and the presence of only one or two semiconductor switches in the current flowing path during each interval of the switching cycle result in lower conduction losses compared to the conventional DCVM Buck PFC rectifier. The DCVM operation offers additional advantages such as: zero-voltage turn-off in the power switches, zero-voltage turn-on in the output diode, and continuous input current. Hence, the electromagnetic interference (EMI) noise emission is minimized. The converter achieves high power factor naturally with low total harmonic distortion (THD) in the input current. Theoretical analysis and experimental results for 100 W/48 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> at 100 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> line voltage are provided to evaluate the performance of the proposed scheme. The measured conversion efficiency reached 96.4%.

Buck-buck/Boost power factor correction (PFC) converter is a great choice to compensate the inherent dead zones in the input current of buck PFC converter. However, whether the converter operates with traditional constant on-time control in critical conduction mode (CRM) or with conventional constant duty-cycle control in discontinuous conduction mode (DCM), the power factor (PF) is low, especially at low input voltage. Therefore, fixed on-time ratio control (FOTRC) and fixed duty-cycle ratio control (FDCRC) are proposed for CRM/DCM buck-buck/boost PFC converter to achieve high PF, respectively. Both control methods maximize PF over wide input voltage range by adjusting on-time or duty-cycle of buck/boost mode and buck mode. Compared with the traditional controls, the proposed control methods also have advantage of increasing efficiency. Furthermore, for improving dynamic response performance, smooth and rapid dynamic response control (SRDRC) is put forward, which can reduce the regulation time and output voltage overshoot/undershoot when the load or input voltage changes abruptly. In addition, the implementation circuits combining FOTRC/FDCRC and SRDRC are designed. Two prototypes have been built and tested in the lab to demonstrate the validity of the theoretical analysis.

The Power Factor Correction (PFC) in Switched Reluctance (SR) motor is discussed in this article. The SR motors are applicable for multiple applications like electric vehicles, wind mills, machineries etc. The doubly salient structure of SR motor causes the occurrence of torque ripples, which affects the power factor of the motor. To improve the power quality, the power factor has to be corrected and the ripples have to be minimized. In order to achieve these objectives, a novel power factor correction (PFC) method is proposed in this work. Here, the conventional Diode Bridge Rectifier (DBR) is replaced by a Bridgeless Hybrid Resonant (HR) converter, which assists in improvising the output in a wider range. The converter is chosen because of having variety of beneficial measures including high gain. The converter’s output is fed to the SR motor by means of an asymmetric Bridge Resonant (BR) converter. The proposed converter operates in continuous mode of conduction with the switching frequency of 10 KHz. A hysteresis current controller and Proportional Integral (PI) controller are utilized for reducing the harmonics in the source current along with the regulation of output voltage. In addition, the speed control of SR motor is accomplished by means of the Whale Optimization Algorithm (WOA) assisted PI controller. The proposed methodology is effective for the control of unity power factor, torque and current ripples. The Total Harmonic Distortion (THD) of the source current is also minimized, which suits the standard of International Electrotechnical Comission IEC 61000-3-2. By this methodology, the power factor of 0.99 is achieved with 97% efficiency and 3.92% THD. The proposed methodology is validated in simulation by MATLAB and in hardware by FPGA Spartan 6E.

There is a need to improve the power quality of the grid as well as the power factor implied on the grid due to the nonlinear loads connected to it. A new single phase bridgeless AC/DC power factor correction (PFC) topology to improve the power factor as well as the total harmonic distortion (THD) of the utility grid is proposed in this research. By eliminating the input bridge in conventional PFC converters, the control circuit is simplified; the total harmonics distortion THD and power factor PF are improved. The controller operates in multi loop fashion as the outer control loop calculates the reference current through innovative filtering and signal processing. Inner current loop generates PWM switching signals through the PI controller. Analytical derivation of the proposed converter is presented in detail. Performance of the proposed PFC topology is verified for prototype using PSIM circuit simulations. The experimental system is developed, and the experimental results agree with simulation results.

This paper introduces a novel algorithm for implementing the digital control method for the single power factor correction (PFC) rectifier. The switching frequency of power semiconductor is variable under different load conditions. The duty cycle is calculated based on digital non-linear control (DNLC) method without the input voltage-sensing circuit. Simulation results of a boost power PFC prototype point out that high power factor and low input current total harmonic distortion (THD) are achieved using proposed control strategy.

A single-stage single-switch (S4) converter integrating a buck-type power factor correction (PFC) cell and a buck-type dc-dc output cell is presented in this paper. The most attractive feature of the proposed S4 converter is that, its input power factor (PF) always keeps in constant even when the input voltage and the load change. Besides, the proposed converter also preserves the advantages of those existent S4 converters, such as the low voltage stress across the intermediate capacitor, low current stress of the switch and high step-down output voltage. These advantages make it cost-efficient and highly suitable for the low power and non-isolated applications. In this paper, the operational modes and circuit design are given, and a prototype is also built to show the validity of the analysis.

AC-DC power factor correction (PFC) single-stage converters both PFC and power conversion are done at the same time using a single converter that regulates the output. While using Switch Mode Converters (SMRs) for conversion from AC to DC, it enhances harmonics of the fundamental frequency at the input source thus increases the total Harmonic Distortion (THD) at the input. In this situation, we lose more power than required for a specific Load. So we need to design such a control system for this converter which could help us reduce the THD at input. I have tried to simulate boost type power factor converter circuit in order to improve the input. Here I have applied average current mode control because of many advantages over other techniques such as high noise immunity and stable operation. Firstly I have simulated only single bridge rectifier without any converter to see the result and THD at input and then I have applied open loop converter with single bridge rectifier to see how it affects the input THD and finally I have applied a converter with current and voltage control loops so that to improve the input THD. A step change at Load end is applied and the result is displayed so that to show the response of the system to be stable.

When a power factor corrector (PFC) is designed with a fast output-voltage feedback loop, the study of the power stage varies in comparison with the one carried out with a slow output-voltage feedback loop. This is a consequence of the voltage ripple that appears in the control signal. The static behaviour of a PFC with a fast output-voltage feedback loop is studied in this paper using two parameters: the module of the relative voltage ripple on the control signal and its phase angle. The total power processed by the PFC depends on these parameters, which do not change with the load and which determine the Total harmonic distortion (THD) and the power factor (PF) at the input of the PFC. Furthermore, these parameters also determine the maximum power that can be processed by the converter while still complying with EN 61000 -3 - 2 regulations for class A and class B equipment. When the converter must comply with the aforementioned regulations for class C or class D equipment, however, the compliance does not depend on the power processed by the PFC and not all the possible combinations of the relative ripple of the control signal and of its phase angle manage to comply with these regulations. As regards the bulk capacitor, its value for a given value of the output voltage ripple is also a function of both the aforementioned parameters. Finally, the study was verified by simulation and in a prototype.