Design System on Chip PreAmp Embedded on Electrocardiograph Based 0,35 CMOS Technology

This paper presents a case study on back gate or body bias variation on the performance of a two stage Class AB Folded Cascode operational amplifier in 22nm FD-SOI (fully depleted silicon on insulator) technology. The back gate bias is varied on each of the op-amp (operational amplifier) building block and its impact on the overall op-amp performance is observed. Finally the performance of the op-amp with back gate bias and without back gate bias are compared. The primary output parameters measured are open loop gain, unity gain bandwidth, settling time (12 bit), output range, phase margin and power consumption. While most of the parameters remain nearly constant, or do not change much, there is a tuning range of 6dB for open loop gain, the input range of 325mV can be shifted by around 110mV and settling time can be varied by 15%.

A novel three-stage CMOS operational amplifier (Op-amp) with high phase margin and high GBW is presented in this paper. The proposed Op-amp has the capability of driving large capacitive loads. Design of frequency compensation network for multistage CMOS Op-amp is always a big concern for researchers as design of compensation network is not quite simple and occupies large space on chip. Compensation network exploited exclusively for this Op-amp has an amalgamation of a very small valued single miller capacitor and differential amplifier and the network has been put in feed forward path. Use of smaller miller capacitor is preferred for low die area on chip and circuit complexity. All transistors of the proposed amplifier are biased by using supply voltage only without using any external current source. The simulated three stage Op-amp exhibits an open loop gain, the unity-gain bandwidth and phase margin as 122 dB, 2.77 MHz and 82.61° respectively. All simulations are done using 0.18 um technology with a 1.8V power supply.

Guaranteeing the reliability of cyber-physical systems (CPS) requires analog integrated circuits for correct functioning. Analog integrated circuits capture the continuous signal and amplify the signal for further processing in CPS applications. This paper presents the hybrid swarm intelligence based approach for determining the optimal transistors sizes and bias current values of CMOS differential amplifier and an operational amplifier. We proposed the simplex search based global optimization method called a hybrid grey wolf optimization (GWO) for solving amplifiers circuit sizing problems. Simplex and GWO techniques were combined to improve the local search capabilities of the optimization method. Our main aim is to optimize the transistor size and bias current values using hybrid GWO algorithm for an optimal design of the CMOS amplifiers. CMOS 180 nm technology was utilized to finding the circuit performance using proposed optimization approach. Simulation result shows that the proposed method provides the better result for circuit performance parameters such as DC gain, phase margin, unity gain bandwidth and power dissipation.

Operational Transconductane Amplifier (OTA) is a fundamental building block of analog signal processing application. This paper demonstrates a wide-linear-range low voltage subthreshold-mode based fully differential OTA using bulk-driven technique. The proposed OTA is linearly tunable with the feature of low distortion and high output impedance. The open loop gain of OTA is enhanced through use of improved Wilson current mirror. The OTA provides an increase in its linearity to about ±1.9 volt. The open loop gain is enhanced to 65dB at unity gain bandwidth (UGB) of 609.46 KHz. The proposed OTA operates at 0.9 volts and power consumption of the OTA remains in range of few hundreds of nanowatts. The OTA analysis has been performed in a standard TSMC 0.18 micrometer technology on BSIM 3v3 model using ELDO Spice Simulator.

This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

This paper presents a fully on-chip differential charge amplifier for microelectromechanical systems (MEMS) piezoelectric sensors in 22nm fully-depleted silicon-on-insulator (FDSOI) technology. MEMS piezoelectric sensors generate small charge signals in response to mechanical stress which requires a highly sensitive and low-noise charge amplifier to accurately convert the signal. A charge amplifier topology is adopted, using an N-boosted folded-cascode operational transconductance amplifier (OTA) and a fully differential difference amplifier (FDDA) with back-gate common-mode feedback (CMFB) circuits as main stages. The proposed design also incorporates pseudo-resistors and on-chip capacitors in the feedback network to maintain the desired impedance while ensuring compact integration. Post-layout simulations confirm the high performance of the system blocks, achieving a 93.3-dB open-loop gain and 94.1-MHz gain-bandwidth for the gain stage, and a small-signal attenuation of 296.6 mdB with a 458-MHz bandwidth for the driver stage. The integrated charge amplifier achieves a closed-loop gain of 45.6 V/V, a high-pass cutoff frequency of 70.8 Hz, and consumes <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{285.6}\ \mu \mathbf{W}$</tex>. These results validate the design's suitability for high-precision, low-power MEMS sensor interfaces.

This paper presents the design and characterization of a fully-differential intermediate frequency (IF) filter based on an operational transconductance amplifier (OTA) with 6th order Butterworth bandpass characteristic. The designed 2-stage BiCMOS OTA can be treated as an operational amplifier (OPAmp) together with its output resistance. The combination exhibits an open-loop voltage gain of 75 dB and high gain-bandwidth product (GBP) of 5.8 GHz, while stability is achieved with a worst case phase margin (PM) of 54° from a low bias-current of only 520 µA. The multiple-feedback filter (MFB) elements for the target Butterworth frequency response are determined with circuit analysis based on an ideal OTA transfer function. The filter center frequency is set to 60 MHz, whereby a measured −3 dB-bandwidth of 15.5MHz is achieved. To enable the operation within an on-time of 200 ns the filter is able to settle at ±1 dB of its steady state amplitude in less than 115 ns. The filter was fabricated in the IHP 130nm BiCMOS technology and requires a current of only 1.6mA from a 2.5V-supply including all bias circuits.

In this paper, the design of low-power, high-speed, two-stage, indirect frequency-compensated operational amplifier is presented. The OPAMP employs split-length devices and class AB output stage. Split-length technique is employed both in load device as well as in differential-pair device. The split-length device enhances the phase margin (PM) and unity gain bandwidth (UGB) while maintaining lower supply voltage. The class AB output stage provides a faster settling time and reduced power dissipation. Simulations of the proposed circuits were carried out in cadence specter on 180-nm process technology at a supply voltage of 1.6 V. The proposed split-length current mirror load OPAMP exhibits power dissipation of 82 µW, UGB of 43.26 MHz, and PM of 79.25°. Similarly, the proposed split-length differential-pair OPAMP exhibits a power dissipation of 78 µW, UGB of 49.71 MHz, and PM of 85.34°.

The Electronic Design Automation (EDA) tools have achieved high degree of maturity and reliability over the years for digital design. The design of analog circuits is a challenge attributed to the existence of multi-dimensional tradeoffs among multiple analog performance metrics like gain, bandwidth, power dissipation, supply voltage, input/output impedances, linearity, voltage swings and noise. The analog design proves to be a significant bottleneck in a System on Chip (SoC) implementation due to lack of automation techniques. To address this issue, the algorithms of the functioning of human brain or soft computing techniques can be gainfully deployed. This work proposes an integrated MaxFit Genetic Algorithm (GA) and GA-SPICE framework to achieve multi-objective optimization of analog design automation. The design of two-stage op-amp is demonstrated in this framework to optimize the objectives of open-loop DC gain, phase margin, unity gain-bandwidth, slew rate, power dissipation and area. The design is performed by proposed MaxFit GA programming of op-amp design equations in MATLAB environment and the design is transmitted seamlessly to LTspice to perform SPICE simulations for design verification. The dynamic fitness evaluation on SPICE generated performance metrics at each iteration of GA programming by transmitting them to MATLAB environment enhances the robustness of analog design significantly.

Differential amplifier is an analog component. which is used as an amplifier whenever a circuit contains more than one input. A differential amplifier is a basic primitive component in an operational amplifier. Differential amplifier contains three legs. In which two legs for the input signal to be amplified, the third leg used as output. The differential amplifier can be configured by bipolar technology or with Metal oxide semiconductor technology also. When the input non-inverted leg which acts as a comparator is applied as input, if any signal applied to invert leg of the differential amplifier it will be used as an amplifier. In this proposed article, the operational amplifier with high gain of 72dB is implemented, the Slew rate of 122 V/µs, Gain bandwidth product of 4.60 MHz Dual-stage operational amplifier will enhance the amplification in a better way when the single-stage amplifier is compared In this article, a dual-stage operational amplifier using CMOS 45nm Technology is implemented.

We present in this paper a low-noise, low-power CMOS operational transconductance amplifier designed for the preconditioning stage of implantable neural recording microsystems. The proposed single-stage amplifier utilizes a combination of recently published techniques, including cross-coupled devices in a recycling folded-cascode topology with positive feedback, to achieve high DC voltage gain and unity-gain bandwidth while minimizing power consumption. A mixed N-type and P-type MOSFET input stage enhances input common-mode performance. Designed and implemented in a 0.18-µm CMOS process with a 1.8 V supply, post-layout simulations demonstrate an open-loop voltage gain of 97.23 dB, a 2.91 MHz unity-gain bandwidth (with a 1 pF load), and an input-referred noise of 4.75 μVrms. The total power dissipation, including bias circuitry, is 5.43 μW, and the amplifier occupies a chip area of 0.0055 mm2. Integrated into a conventional neural recording amplifier configuration, the proposed amplifier achieves a simulated input-referred noise of 5.73 µVrms over a 1 Hz to 10 kHz bandwidth with a power consumption of 5.6 µW. This performance makes it suitable for amplifying both action potential and local field potential signals. The amplifier provides an output voltage swing of 0.976 Vpp with a total harmonic distortion of −62.68 dB at 1 kHz.

An operational transconductance-amplifier (OTA) is mainly designed for low voltage and low frequency applications such as for the medical applications. The Operational Transconductance Amplifier (OTA) is the part in an analog integrated circuits for many wireless applications such as binural hearing aids. High gain is becoming more important in miniature devices because this parametric form provide the significant outcomes, so it becomes a challenge to design a low power OTA. The proposed design helps to generates the design parameters such as the Width/Length ratio are given to design specifications, such as, gain, unity gain-bandwidth, phase margin. This paper is mainly proposed for the low frequency application using transconductance amplifier.

An ultra-low-voltage ultra-low-power operational transconductance amplifier (OTA) using dynamic threshold MOS (DTMOS) technique is presented in this paper. The proposed topology is based on a bulk and gate driven input differential pair employs a gain-stage in the Miller capacitor feedback path to improve the pole-splitting effect. The circuit is designed in the 0.18μm CMOS technology. The simulation results show that the amplifier has a 91dB open-loop DC gain and a unity gain-bandwidth of 111.4 kHz while operating at 0.4V supply voltage. This technique show remarkable enhancement in unity gain-bandwidth and also in DC gain compared to the bulk driven input differential pair technique. The total power consumption is as low as 386nW which makes it suitable for low-power bio-medical applications.

With the development of integrated circuit technology, the size of electronic equipment continues to reduce, and speed continues to increase. Operational amplifiers are the key circuit in analog ICs, and the required performance of operational amplifiers is also increasingly high, research and design of high-performance operational amplifiers has become one of the key topics of today's research. A CMOS two-stage operational amplifier with high unity-gain bandwidth is analysed and designed with an appropriate Miller-compensation technique in this research to improve the frequency characteristics and stability. The design is based on 180nm CMOS process. Its performance is simulated and analysed in Cadence software environment. The performance parameters are shown by simulation results that the amplifier has a gain of 61.81dB, a GB (unity-gain bandwidth) of 907.42MHz and a phase margin of 75.02°. The experimental results show that it achieves high unity-gain bandwidth while ensuring gain and stability. Through this study, the principles of two-stage operational amplifiers and their compensation as well as the design and simulation are shown in detail in both theoretical and experimental sections.

In this paper, a folded cascode operational amplifier is designed and analysed by using 0.13 µm CMOS technology. Several analyses such as DC analysis and AC analysis are carried out to analyse the performances of the proposed folded cascode op-amp. Through the simulation of Mentor Graphics, under 3.3 V power supply, the circuit’ s DC gain is 32.3590 dB, the phase margin is 83.754 degree with high stability, the bandwidth is larger than 10 MHz, the unity gain bandwidth is as high as 906.8953 MHz and the power dissipation is 86.9774 mW.