Bulk driven OTA in 0.18 micron with high linearity

Current-mode electronically tunable biquadratic filters consisting of only CCCIIs and grounded capacitors

The architecture level design of an impedance matching network is presented for the global system for mobile communication radio frequency (GSM RF) power amplifier module used in a typical cellular handset. Designs for the low and high output impedance of the power amplifier and 50 Ω antenna impedance are considered. Impedance matching network design is presented for a typical low output impedance (Z = 2-j*0.4 Ω) of the power amplifier and 50 Ω antenna impedance and is made adaptive for high output impedance (Z = 7+j*2 Ω). It is shown that the network can be made adaptive to varying output requirements of the power amplifier by tuning the network capacitance toward the antenna end. The architecture level design of a 25 Ω antenna impedance is also presented and shown that that the impedance matching network can be made adaptive, which would require the use of MEMS switches. The adaptive impedance matching networks can be implemented in a passive integration technology with post-processing for MEMS components.

This paper presents a case study on back gate or body bias variation on the performance of a two stage Class AB Folded Cascode operational amplifier in 22nm FD-SOI (fully depleted silicon on insulator) technology. The back gate bias is varied on each of the op-amp (operational amplifier) building block and its impact on the overall op-amp performance is observed. Finally the performance of the op-amp with back gate bias and without back gate bias are compared. The primary output parameters measured are open loop gain, unity gain bandwidth, settling time (12 bit), output range, phase margin and power consumption. While most of the parameters remain nearly constant, or do not change much, there is a tuning range of 6dB for open loop gain, the input range of 325mV can be shifted by around 110mV and settling time can be varied by 15%.

The state-of-the-art energy harvesters that harness environmental kinetic energy toward realizing battery-free Internet of Things (IoT) applications are susceptible to low power density owing to low charge density and high output impedance. Here, a new charge regulation strategy is introduced that simultaneously enhances charge transport rate and the total amount of charges, allowing for achieving a volumetric peak power density exceeding 10 MWm-3. It is demonstrated that such an enhanced performance results from the synergistic cooperation between a transistor-inspired switching architecture that accelerates charge transfer rate whereas minimizing internal impedance and a bio-inspired charge vascular system that enhances the amount of generated charge, together contributing to a torrent-like charge regulation (TCR). The unique TCR strategy as well as the induced high power output endows a fully battery-free wireless sensing and communication platform, highlighting its potential to enable sustainable, distributed battery-free IoT networks in real-world applications.

The most important advantage of a source-gated transistor compared with a field-effect transistor (FET) is its low saturation voltage and high output impedance. Here we model a reverse biased gated Schottky barrier source in hydrogenated amorphous silicon and show good qualitative agreement between the calculated effect of source geometry and measurements. Furthermore, calculations of electron concentration profiles in the source show why the source-gated transistor in hydrogenated amorphous silicon is more stable than an equivalent FET.

In this paper, a new first-order current-mode (CM) universal filter employing two dual output second-generation current conveyors (DO-CCIIs), one resistor and a grounded capacitor is proposed. The proposed filter has low input and high output impedances; thus, it can be easily connected with other CM circuits. It can simultaneously realize first-order low-pass (LP) and all-pass (AP) responses and can provide high-pass (HP) response with interconnection of LP and AP responses. It can be tuned electronically by replacing with dual output second-generation current controlled conveyors (DO-CCCIIs) instead of DO-CCIIs and removing the resistor. It has only a resistor but no capacitor connected in series to X terminal of DO-CCII; accordingly, it can be operated at high frequencies. Also, it does not need any critical passive component matching conditions and cancellation constraints. A number of simulation results based on SPICE program are included to exhibit performance, workability and effectiveness of the proposed filter configuration.

The heartbeat has frequency from 0.1 Hz to 150 Hz. The electrical signal which is resulted from the heartbeat has amplitude of 100μV - 4 mV. In order that the amplitude can be sampled by the ADC, it must be amplified 100 times, thus amplitude amplifier about 60dB it is required. In this research, the researcher designs a System on Chip ECG based on Einthoven method which has 3 Leads, so amplitude can be amplified based on the different voltage of each Lead. Differential amplifier is an initial amplifier that will amplify the difference of two inputs of voltage. Differential amplifier is designed using 3 operational amplifiers (op-amp). Op-Amp A1 and Op-Amp A2 are used for detecting and sampling the difference of two input levels. The function of Op-Amp A3 is to amplify the difference results of the sampled input level. Op-Amp A1, Op-Amp A2 and Op-Amp A3 are designed with offset voltage of Vos ≈ 0V, Open Loop Gain ≈ 66.42 dB, Phase Margin ≈ 400 and Unity Gain Bandwidth ≈ 160.7MHz. Method of the research is design and simulation using 0.35 micro Mentor Graphics technology. Result of the research is a layout of PreAmp for System on Chip ECG with gain of 62.4 dB and 0.034 mm2 area.

In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple mirror/source structure with input and output voltage requirements less than that of a simple current mirror is presented. It can be also used as variable negative impedance converter (variable-NIC) by modifying amplifier transistors' aspect ratios. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Working with power supplies less than 1volt, the proposed circuit provides output impedance greater than LVC current mirror. Such outstanding features of this current mirror as high output impedance~25.3M, low input impedance~44, wide bandwidth~498 MHz, low input voltage ~ 415 mV, low output voltage ~ 149 mV and low current transfer error ~1.3% (all at 10 ¿A) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35 ¿m CMOS technology with Hspice are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror/NIC.

10 - Basic analog electronics: Operational amplifiers

In this paper a new current-mode multifunction filter using opamp compensation poles is presented. The proposed circuit is composed of two internally compensated operational amplifiers (OAs) and five single output operational transconductance amplifiers (OTAs), without using external passive elements. The proposed multifunction filter can realize lowpass, bandpass, highpass and bandstop responses simultaneously all at high output impedances. The circuit is suitable for monolithic implementation either with CMOS or bipolar technologies. All of active sensitivities are low. The performances of the circuits are tested using SPICE simulation program.

We present in this paper a low-noise, low-power CMOS operational transconductance amplifier designed for the preconditioning stage of implantable neural recording microsystems. The proposed single-stage amplifier utilizes a combination of recently published techniques, including cross-coupled devices in a recycling folded-cascode topology with positive feedback, to achieve high DC voltage gain and unity-gain bandwidth while minimizing power consumption. A mixed N-type and P-type MOSFET input stage enhances input common-mode performance. Designed and implemented in a 0.18-µm CMOS process with a 1.8 V supply, post-layout simulations demonstrate an open-loop voltage gain of 97.23 dB, a 2.91 MHz unity-gain bandwidth (with a 1 pF load), and an input-referred noise of 4.75 μVrms. The total power dissipation, including bias circuitry, is 5.43 μW, and the amplifier occupies a chip area of 0.0055 mm2. Integrated into a conventional neural recording amplifier configuration, the proposed amplifier achieves a simulated input-referred noise of 5.73 µVrms over a 1 Hz to 10 kHz bandwidth with a power consumption of 5.6 µW. This performance makes it suitable for amplifying both action potential and local field potential signals. The amplifier provides an output voltage swing of 0.976 Vpp with a total harmonic distortion of −62.68 dB at 1 kHz.

This paper presents floating gate MOSFET (FGMOS)-based second generation differential voltage current conveyor (DVCCII) at low voltage levels. In analog circuit design, the FGMOS transistors are very often used in low voltage circuits, where the reduction obtained in the transistor apparent threshold voltage is of great importance. The given circuit provides very high input impedance at its Y-terminals, low output impedance at X-terminal and high impedance at Z-terminals and consumes less power. This circuit is a powerful building block, especially for applications demanding differential or floating inputs. The circuit behavior has been verified using PSpice simulations for 0.5 μm technology and indicates the excellent performance.

Chapter 7 - Advanced Transistor Amplifier Techniques

An ultra-low-voltage ultra-low-power operational transconductance amplifier (OTA) using dynamic threshold MOS (DTMOS) technique is presented in this paper. The proposed topology is based on a bulk and gate driven input differential pair employs a gain-stage in the Miller capacitor feedback path to improve the pole-splitting effect. The circuit is designed in the 0.18μm CMOS technology. The simulation results show that the amplifier has a 91dB open-loop DC gain and a unity gain-bandwidth of 111.4 kHz while operating at 0.4V supply voltage. This technique show remarkable enhancement in unity gain-bandwidth and also in DC gain compared to the bulk driven input differential pair technique. The total power consumption is as low as 386nW which makes it suitable for low-power bio-medical applications.

In this paper, we propose an analog-to-digital converter (ADC) using a hybrid single-electron-transistor/complementary metal-oxide-semiconductor (SET/CMOS) universal literal gate based on the Coulomb oscillation phenomenon of a SET. The SET/CMOS universal literal gate consists of the SET/resistor inverter and the CMOS inverter, whose input is connected to the output of SET/resistor inverter. Because the CMOS inverter has the high input impedance and the low output impedance, the proposed circuit makes it possible to overcome the disadvantage of the high output impedance of a SET/resistor inverter by connecting its output to any input of CMOS circuit. The circuit has shown high immunity on temperature and can eliminate the background charge effect as applied to ADC. Using SPICE macromodel of SET at 30 K, we demonstrated the performance of a 4-bit ADC, composed of SET/CMOS universal literal gate and capacitive divider. These results can be simply extended to multi-bit ADC.