Development of a bond contribution model for structure: property correlations in dry etch studies

Self-assembly block copolymers have drawn a lot of attention for its great potential on critical dimension (CD) control and line-edge roughness (LER) reduction, which become more and more crucial as the CD of transistors is only tens of nanometers nowadays. In this study, lamellar-forming poly(styrene-b-methyl methacrylate) copolymer which fabricates line patterns was chosen for its ability to provide higher aspect ratio and vertical sidewall profile in template stage, thus more suitable for the following etching process to substrate. A dry plasma etching process using pure oxygen and pure argon plasma as example chemical etching gas and physical etching gas, respectively, was studied. Etching selectivity and lateral etch rate, which are responsible for the final template height and CD loss, had been characterized on a capacitive reactive ion etching tool. The templates formed by the proposed process had high aspect ratios, excellent pattern fidelity, and low LER values. The PS lateral etch rate was small enough to provide a wide process window for retaining the CD of the pattern during the template forming process. Subsequent silicon etching using the PS template made by dry etching process yielded a steep and smooth sidewall profile.

Background: CR-39 nuclear track detectors are widely used in various fields, including science, technology, astronomy, and environmental preservation, to detect and register heavy ions, neutrons, and alpha particles. Objective: This study aims to determine the optimal etching duration for CR-39 nuclear track detectors by comparing etching methods: The wet etching (using a water bath) and the dry etching technique (using dielectric barrier discharge (DBD) plasma). Methods: The traditional etching method involved immersing CR-39 detectors in a sodium hydroxide (NaOH) solution at 70 °C for varying durations. The dry etching method employed employs a non-thermal DBD plasma system to etch solid-state nuclear track detectors (SSNTDs) without the use of chemical solutions. Results: Photomicrographs revealed that tracks from chemical etching became clearly visible after 1 hour and developed at 5 hours. In contrast, the dry etching technique was significantly faster; tracks began to appear after just 1 minute of DBD plasma etching and were fully developed at 5 minutes. The optimum track density for DBD plasma was 20340±56 tracks/mm2 at 3 minutes, whereas the traditional water bath method achieved an optimum track density of 5238.0±5.7 tracks/mm2 at 2 hours. The shorter etching duration in the dry method likely facilitates the emergence of latent tracks without overlap. Conclusions: The bulk etch rate (VB) for CR-39 detectors using the dry DBD plasma etching technique was faster compared to the traditional chemical etching method. This demonstrates the efficacy of the dry etching process in significantly reducing etching time required for etching SSNDs.

Even with the copious advances in logic device fabrication, integration of new channel materials would represent a significant advance in CMOS technology. [1] Successful integration of new channel materials (III-V’s, Ge and SiGe) pose significant challenges for etch technology. Dry (plasma) etch technology can be used to pattern channel materials after they are deposited using an epitaxial process [2]; alternatively channels maybe inserted into bounded (for example an oxide) recesses (for example silicon) fabricated using etch technologies already developed for FinFET and SAQP applications. Less appealing is the use of wet processes that have troublesome crystallographic orientation dependencies. Dry etch technology for most new channel material candidates is not new. [3] Still, with dry etch technology there is the ever-present worry of damage. [4-6] High precision etch technology commonly referred to as atomic later etching (ALE) is an emerging viable option for new channel material integration. [7-10] Some approaches employ non-mainstream techniques such as neutral beam technology [8] or complex precursors. [10] Recent developments reinforce that conventional plasma etch technologies developed using concurrent engineering methods can meet the requirements for 7 and 5 nm logic fabrication. [7,11] This presentation will show how advanced plasma etch technologies provide a path for logic manufacture beyond 7 nm with a realistic picture of the trade-offs that must be handled for the introduction of III-Vs, Ge or SiGe. All in all, etch technologies if successfully implemented for new channel material integration relies of leveraging surface chemistry mechanisms. The presentation will be rounded out with a discussion of how first-principles methods (e.g., DFT methods) can be used to gain insight into important plasma –surface interaction mechanisms. S. Takagi et al., Japanese Journal of Applied Physics 54, 06FA01 (2015) Chen et al,. Nanoscale Research Letters, 7, 431 (2012) Plasma Etching of III–V Nitrides,” by R. Shul, in Processing of Wide Band Gap Semiconductors: Growth, Processing and Applications, 250 (2000), ed., S.J. Pearton F.D. Auret et al., Physica B, 407, 1497 (2012) Kasumandari et al., Appl. Phys. Lett., 103, 033511 (2013) “Dry Etching of Semiconductors at the Nano-and Micro-Scale” by S.J. Pearton in Vistas in Nanofabrication, (2012) A. Ranjan et al., J. Vac. Sci. Technol. A 34, 031304 (2016) S.D. Park et al., Appl. Phys. Lett. 91, 013110 (2007); C. T. Carver et al., ECS J. Sol. St. Sci. Tech., 4 N5005-N5009 (2015) S. M. George, Chem. Rev., 110, 111 (2010) S.D. Sherpa et al., J. Vac. Sci. Technol. A 35, 01A102 (2017)

For logic nodes of 7 nm and beyond, back-end-of-line (BEOL) trench patterns have a critical pitch of less than 40 nm, directly affecting the plasma etch process window of the dual damascene etch process. Feature size dependent etch depth (reactive ion etch, RIE lag), hard mask selectivity, and ultra-low-k (ULK) damage have become significant challenges that must be overcome in order to meet target device performance. Recently, atomic layer etching has been used to widen the plasma etch process window in terms of selectivity and process control [S. Sherpa, P. L. F. Ventzek, and A. Ranjan, J. Vac. Sci. Technol. A 35, 05C310 (2017); T. Tsutsumi, H. Kondo, M. Hori, M. Zaitsu, A. Kobayashi, T. Nozawa, and N. Kobayashi, J. Vac. Sci. Technol. A 35, 01A103 (2017)]. In this work, the impact of a quasiatomic layer etch (QALE) process, a conventional continuous wave plasma, and a pulsed plasma process on ULK materials were investigated to determine the benefits of an ALE process approach for BEOL etching. Both blanket ULK film and patterned ULK samples were used for this study. The ULK etch damage from each process was characterized using Fourier transform infrared spectroscopy and x-ray photoelectron spectroscopy on three different ULK films. From patterned samples, it was determined that QALE could be used to successfully suppress RIE lag in low-k materials at advanced pitches, while keeping low-k damage to a minimum. In addition, the QALE technique showed improved hard mask selectivity and resulted in lower line edge pattern roughness. Based on this study, the authors concluded that QALE is a powerful plasma etch method to overcome BEOL etch challenges at advanced pitches.

Plasma etching or Reactive Ion Etching (RIE) is the workhorse for patterning of semiconductor devices since the early 1980-ies when it replaced wet etching in manufacturing. Today, RIE is reaching levels of performance which were unimaginable back then. At the same time, etching technologies such as Atomic Layer Etching (ALE), radical, dry vapor and Ion Beam Etching are finding their way into manufacturing for certain applications. We will present an overview of dry etching technologies used in semiconductor manufacturing. The emphasis is on the elementary surface processes and how they impact the performance on the wafer. We will start from less complex etching technologies which use just one kind of etching species, such as neutrals, radicals or ions. Then we combine these techniques into cycling processes which leads to the discussion of ALE. The highest level of complexity is reached in RIE with simultaneous species fluxes. Reactor designs for the various etching technologies and process control will be covered. Finally, and an outlook into the future of semiconductor device etching will be given.

A new Portable Conformable Mask (PCM) bilayer process has been developed that uses Reactive Ion Etching (RIE) for development of the bottom PMMA layer to produce steep resist profiles. This new process uses a gas mixture of ( C2F6+CHF3 ) that effectively removes the PMMA resist, interfacial layer and that has a high rate of anisotropic development for the bottom PMMA layer --- combining the advantage of performance on a trilayer process with the relative simplicity of PCM. The development rate of the top resist layer is very small and result in very little thickness loss of the top imaged positive resist. The top layer of positive photoresist remains intact to protect the PMMA during etching process. This eliminates the requirement of an intermediate barrier layer or special resist materials. For the additional protection during etching process, the resist can be hardened by a deep ultraviolet ( DUV ) exposure after RIE development of PMMA and it is observed that small amount of DUV exposure effectively improves the plasma resistance on this resist structure. This new PCM process has been used for the dry etching process of aluminum film using a gas mixture of BC13+CF4+02. An optional layer of sputtered amorphous silicon can be used between the aluminum and the PMMA to act as an antireflection layer. Using this process and an EATON-OPTIMETRIX MODEL 8605H wafer stepper, 0.6μm line and space of equal width have been exposed and etched into 9000A of aluminum film. Critical process steps are given, the effects of variation in process parameters are described, and SEM photographs of the final results are shown.

Up until the late 1960s, chemical etching, also called wet solvent etching, was the key technology to integrated circuit manufacturing. Indeed, from the standpoint of manufacturing, wet etching provides low cost and often infinite selectivity. But, inherent limitations in wet etching preclude the use of this technique for micron and submicron pattern sizes. The most serious limitation is that of isotropic etching, which results in undercutting of the mask material and hence limits the minimum size of the pattern. To obtain high-density packing of microelectronic circuits, anisotropic etching is essential. By the early 1970s, CF /02 dry etching was widely adopted for patterning. It was widely recognized that dry etching offered the possibility of a vertical etch rate that greatly exceeded the horizontal etch rate (namely anisotropic etching). As a result, these dry etching techniques, which can generate anisotropic etch profiles, came into prominence. Dry etching soon began to appear in IC fabrication. However, these dry etching technologies, like wet processes, had their resolution limited by undercutting, and other, even more anisotropic etching techniques appeared. Among these were reactive ion etching (RIE). The RIE technique which has been widely adopted for IC fabrication until now provides moderate selectivity, etch rate and high anisotropy. In the mid-to-late 1970s, research began on a dry etch technique which would combine the positive features of RIE with directional bombardment of the surface by ions accelerated through electrostatic sheaths. Figure 1.1 shows how integrated circuits have evolved and how the number of individual components per circuit has increased with time. It is seen in the figure that the component density of IC circuits has doubled every year and this yearly doubling rate has been maintained from the first IC in 1960 until recently. At the same time, the design feature size has shrunk from 6 μm to 0.8 μm in the last 15 years, and the smallest dimensions are expected to decrease to 0.1 μmin the near future.

Patterning of silicon is necessary in a number of microelectronic and micromechanic applications. Plasma processes, such as reactive ion etching, play an important role in VLSI and nanotechnology applications. The charged particles impinging onto the semiconductor surface may cause radiation damage, such as crystal defects of different dimensionality. In plasma etching processes resist patterning and a large number of processing steps are needed to perform etching. The laser-induced dry etching (LDE) process offers the possibilities of direct pattern transfer by mask projection, anisotropic etching with negligible damage, and etching with very high selectivity. Modifying the LDE-process by applying a microwave-excited gas results in more radicals and an increased etch rate. Some authors use Cl2 as the processing gas during the microwave-assisted laser dry etching (MALDE) with excimer laser radiation (248 nm) [1,2]. In this case the etch rate of Si(100) is below 1 A/pulse.

The incorporation of dry etch processes for mercury cadmium telluride (HgCdTe) infrared device fabrication is becoming critical for the infrared community as we advance toward the production of high-density devices. Dry etch processes are cleaner than wet etch processes. In addition, dry etches are highly anisotropic and are capable of producing the small features required by the more advanced device architectures. However, the incorporation of dry etch processes into device fabrication often affects the surface quality, producing roughened surfaces and variations in composition. Consequently, the identification of suitable dry etch processes to produce high quality infrared devices is essential. In this investigation, three different plasma etching tools (reactive ion etching, electron cyclotron resonance, and remote microwave) were used to etch HgCdTe with hydrogen. The hydrogen interaction with HgCdTe at similar etch depths was examined with spectroscopic ellipsometry and atomic force microscopy. Variations in surface roughness and composition obtained when etching with the three plasma etching tools are reported and the significance of energetic ions on surface quality is discussed.

In this work, an alternative dry etching approach for parylene AF4 is presented based on a photoresist soft mask, which results in a relatively simpler, faster, cheaper and environmentally friendly process in comparison to the typical dry etching process with a hard mask. 2.5 µm thick parylene AF4 was deposited on a silicon (Si) substrate by vapor deposition polymerization (VDP). A 5 µm thick photoresist was used as a soft mask, while parylene AF4 patterning was done using an oxygen (O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> )-argon (Ar) inductively coupled plasma reactive ion etching (ICP-RIE) process. The AF4:photoresist selectivity was around 1 while the AF 4 etching rate was roughly 275 nm/min for an Ar/02 ratio of 0.1 at 20mTorr and ICP:CCP powers of 1000W:50W respectively. The influence of the ICP plasma parameters on the AF 4 etching rate was investigated and the results suggested a predominant oxygen radicals-based reactive chemical etching mechanism.

We have examined the reactive ion etch (RIE) resistance of two families of 193 nm photoresist candidates, poly(methacrylates) and vinyl-polymerized poly(cyclic olefins), in three RIE processes. Correlation of these measurements to polymer structure and composition using known methods (Ohnishi and Ring Parameter fits) was moderately successful in demonstrating global trends but proved generally inadequate for providing quantitative predictions. To address this shortcoming, we have developed a new empirical structural parameter which provides a much more precise model for predicting RIE rates within a given family of polymers. The model is applicable across polymer platforms, with two caveats: (1) The methacrylate and cyclic olefin families examined to date fall on essentially parallel, offset curves when examined with the new model, (2) The offset between polymer family curves is RIE tool- and process-dependent. While these caveats imply a setback to the idea of a truly `universal' model, they may in fact represent a powerful and unanticipated feature; the model appears to separate chemical RIE processes which affect individual functionalities within a polymer from predominantly polymer-family dependent processes such as global backbone degradation. In the course of conducting these studies, we have encountered several potential pitfalls in the measurement of etch rates. These illustrate the complex nature of plasma: resist interactions and highlight the careful experimental design and controls that are required if meaningful RIE rate comparisons between polymer and resist families are desired.

This thesis describes the development of a dry plasma etch smoothing technique to replace the conventional Chemical Mechanical Polishing process within a device manufacturing scheme in the semiconductor industry. An important semiconductor manufacturing process is 3D wafer packaging, which allows vertical stacking of wafer die. 3D wafer packing represents a significant component of the total wafer level processing cost. A critical step in the 3D packaging process flow is the Chemical Mechanical Polishing process. Replacement of the CMP process step with a corresponding dry etch can yield significant time and cost savings. This is achievable through reductions in metrology and wafer handling requirements and lower volumes of materials needed for plasma-etch based processes compared with CMP. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200 nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6 nm is demonstrated, which is comparable to a virgin silicon wafer. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where these surface scratches are falsely identified as defects. The quality of the plasma polished surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification process followed by a roughness reduction iteratively, to produce a smooth surface without visible grind marks. Further work describes the application of the smoothing process to microneedles, with the aim of improving the process flow. Smoothing of silicon carbide has been performed. Finally, an extension of the TSV reveal process is described, called extreme thinning, with the development of a predictive model to minimize final total thickness variation. Silicon smoothing can also be beneficial to this application.

In information and communication technology (ICT) equipment indispensable for modern society, semiconductor memories occupy the main position of storage memories, working memories, and e-memories in logic blocks. In current semiconductor memories, rapid increase in the power consumption is most serious issue, as the more energy-saving is strongly required for ICT technology. From above view point, STT-MRAM and its application such as NV-Logic are aggressively studied in the world and many excellent results were published. However, almost results of STT-MRAM were fabricated by ion beam etch (IBE) process. Therefore, for higher density STT-MRAM's mass-production under wide patterning process margin and high TAT, plasma based reactive ion etch (RIE) process technology for MTJs is needed. In this invited paper, it is reviewed our previas results regarding STT-MRAM and NV-Logic fabricated by RIE process as shown in Fig. 1. It is shown that STT-MRAM and NV-MCU etc. were successfully worked under extremely low power consumption. Moreover, it is reviewed our previas results of RIE process technology itself. We presented process and device results from a developed chemistry set which significantly reduces the etch damage compared with conventional chemistry. An etched MTJ stack profile is included in Fig. 2. The damage caused by RIE on the magnetic properties of the CoFeB free layer in a MTJ with a perpendicular easy axis (p-MTJ), and on the TMR ratio of CoFeB-MgO p-MTJs was characterized to identify its root cause. Fig. 3 includes TMR data from a selection of different chemistry sets. Our developed chemistry is based on learning that it is N and H radicals that are the primary source of damage. With our developed process, high TMR ratio was achieved with very slight degradation. We report our chemistry, its underlying concept, resultant MTJ profiles, device electrical and magnetic properties. Finally, we summarize the MTJ damage mechanism useful for bringing MTJ fabrication etch technology to maturity.

Fabrication of high aspect ratio metal patterns without rabbit ear shaped defects on rigid Si and flexible polyethylene terephthalate (PET) substrates was demonstrated. This process is composed of UV nanoimprint lithography (UV-NIL), resist pattern transfer step, and lift-off process. The imprinted resist pattern with a positive pattern profile on a water soluble polyvinyl alcohol (PVA) coated transparent substrate was transferred to Si and PET substrates in order to create an undercut profile for the high fidelity lift-off process using an UV curable adhesive. After the pattern transfer step, the PVA coated substrate was released by water soaking. The adhesive residue on the substrate was removed by short O2 reactive ion etching (RIE) without significant change of the resist pattern profile. Subsequently, the metal film was deposited by e-beam evaporation on the sample and the resist pattern was removed by acetone solution. As a result, the metal patterns with 250 nm of linewidth and 80 nm of thickness were formed by this process on Si and flexible PET substrates without rabbit ear shaped defects.

Mask erosion is not significant in tn-layer lithography where the etching mask is Si02; however, mask erosion may significantly affect etching profiles and process latitudes during the pattern transfer step in bi-layer lithography. We discuss the effect of selectivity, wall angle, layer thickness, and etching anisotropy on line-width loss in bilayer lithography. Predictions from the kinetic theory of bombardment induced interface evolution are compared to experimental pattern transfer results for electron beam exposed poly(trimethylsilylmethyl methacrylate-co-m,pchloromethylstyrene). The interface evolution model describes bombardment induced etching by an axisymmetric angular distribution of energetic particles where the yield per incident particle is a function of energy and angle relative to the surface normal. Kinetic theory is used to relate the energy and angular distributions incident on the substrate to the pressure, the voltage drop across the plasma sheath, the sheath thickness, and the cross sections describing the collision processes. The rate controlling step for the organosilicon polymer is assumed to be Si02 sputtering as predicted by the steady-state model of organosilicon polymer etching. The 5i02 sputtering yield is assumed to be a separable function of.energy and angle with a sputtering threshold of 50 eV. The etching yield of the organic planarizing layer is assumed to be proportional to bombardment energy and independent of angle. The angle dependent yields in the upper layer result in a facet that propagates down from the upper edge of the resist profile. This facet has no effect on process latitudes if less then F30% of the upper layer is consumed during the pattern transfer step; however, faceting results in rapid line-width loss if more than 30% of the upper layer is consumed. Under nearly optimized exposure and etching conditions, the experimental line-width loss during pattern transfer was less than 20% of the nominal width for features with nominal dimensions down to 0.25 zm.