Development of LED Package Heat Dissipation Research.

Phosphor layer geometry is one of key factors which determine the optical performance of white LEDs in LED packaging. In order to gain the optimal phosphor geometries, a method for forming different geometries of phosphor layer based on microfluidics and structure control is reported. Through controlling the slanting angle of the reflector cups on basis of conventional dispensing coating process, different curvatures of phosphor layers can be realized to meet the packaging requirement. The numerical simulations and experiments on phosphor slurry dispensing into reflector cups with different slanting angles were conducted. The results reveal that different curvatures of phosphor layers can be easily obtained by varying the slanting angle of reflector cup. By the present method, we packaged several LED samples, one of optical parameters, angular color uniformity (ACU) was measured. The results reveal that the good ACU can be gained using this simple method to form flat phosphor layer in the reflector cup packaging structure.

With the increasing output power of LED chip, heat dissipation analysis and design of high-power LED has become one of the key technologies of LED packaging. In this paper, the three-dimensional packaging model of high-power LED is established. The finite element method is used to simulate the temperature field distribution of LED. The influence of bonding material and substrate thickness on the heat dissipation of LED package is analyzed by changing the relevant parameters of LED package, and this method has a certain guiding significance on optimizing the LED package.

Thermal management of multi-chip module high power LED (MCM-LED) packaging is one key technology to the development of the reliable MCM-LED. In this paper, referring to MCM technology applied in IC packaging, and aiming at high power flip chip GaN-based LED packaging, the thermal analysis of MCM-LED is studied. Firstly, both a 2×2 flip chip LED array that is mounted on a bracket and heat dissipation packaging structure with the performance parameters of related materials are designed. Secondly, based on principle of heat transfer, the thermal resistance network of MCM-LED heat dissipation system is expressed, and the thermal resistance of cooling channel is theoretically calculated. The total thermal resistance and the junction temperature of LED chip of theoretical value are about 6.53 K/W and 77.2°C respectively. Thirdly, based on numerical analysis method, a 3-D finite element model (FEM) is developed. The temperature distribution in the chips and packages are shown, and junction temperature and total thermal resistance of simulative value are 82.12°Cand 7.14 K/W respectively. Finally, by means of orthogonal design of experiments, the optimized prototype structure and its related parameters are concluded. Aiming at the related material and structure parameters of MCM-LED packaging, the diameter of bump is the most important factor to thermal performance, following by the bonding layer material, chip size, the thickness of bonding layer and chip spacing.

The mania for mobility applications such as smart-phones, tablet PCs, and personal computers is sweeping all over the globe. In order to insure the performance of a new product, the Design for Manufacture (DFM) plays an important role on a package design both in research stage and mass product stage. The substrate process capabilities, assembly process capabilities, material properties, and package structure are the main factors for DFM. In this paper, a high density DSP (Digital Signal Processing) package is showed as an example for the DFM methodology. For this typical high density WB-BGA package, the warpage control is the key point for DFM not only in substrate process but also in assembly process. The molding compound (MC) is used for protecting die. Molding or dispending process is the main step for assembly process. The coefficient of thermal expansion (CTE) mismatch and the material shrinkage cause the substrate deformation. If the substrate deformation large enough, it will affect cold solder joint between substrate and PCB (Printed Circuit Board), and the electrical performance and reliability. To evaluate the deformation by molding or dispensing process, the cooling down stage from 125 °C to 25 °C was simulated by EDA tool. The warpage of test samples with different molding height were measured here to estimate the real DSP package design. The difference of simulation data and measurement data are little. If the molding height is large enough, the structure deformation mainly depends on the molding structure. To improve the warpage, a copper ring is used in dispensing technology for DSP package. The significant signals were tested by oscilloscope and logic analyzer to verify the performance of DSP package, and the performance of the DSP was satisfied with the target.

The continuous scaling down of devices has led to increase use of smaller interconnect features that can increase the interconnection delays. In order to reduce such interconnection delays, low-k dielectric has been introduced, and then for advanced devices that require further reduction in delays, porous structure called ultra low-k (ULK) material has been developed. The porous structure of ULK dielectric has poor elastic stiffness and fracture resistance that is vulnerable to catastrophic failures such as ULK cracks or delamination during packaging processes or reliability tests. A flip chip test vehicle has been designed and prepared to experimentally characterize the ULK related failures such as white bumps, which are localized ULK cracks found underneath the flip chip bumps. Stresses acting on ULK layer have been analyzed using finite element methods with global and local modeling. Test results show packaging material set with low coefficient of thermal expansion (CTE) substrate and high glasstransition temperature underfill improved the structural integrity of chip-package assembly by reducing the stresses on ULK layer caused by CTE mismatch between chip and package substrate. Cu pillar bumps are more susceptible to white bump failure, and large bump size can reduce the stress on the ULK layer. Package structure with thinner chip has shown to be effective in reducing white bump failures. Besides the package material and geometry, structure and material of the back-end-of-line (BEOL) layer has also shown to be critical. White bump failures were concentrated underneath the pattern where some vias were missing. In view of ULK interface, etch stop layer material showed influence on white bump failure ratio. Proper selection of package materials and structure as well as carefully placed metal, via density and ESL material are critical in achieving structurally stable chip-package-interaction.

For the case of the white LED (phosphor converted), the temperature affects phosphor in addition to chip and package. The heat can cause the decrease of the phosphor performance as well as the irreversible damage to the phosphor. In this study, the effect of phosphor thermal configuration on the degradation rate has been investigated experimentally and verified by the theoretical simulations. Two different configurations have been tested. One is die‐contact phosphor layer and the other is remote case. The experimental result shows that the LEDs of the die‐contact phosphor layers exhibit lower degradation rate than those of the remote phosphor layers. The thermal simulation considering the heat generation from the phosphor (energy converting loss) shows similar results. The temperature of remote phosphor layer is higher than the die‐contact case. High temperature causes rapid degradation of phosphor. As the power consumption of LEDs increases, the heat generation from the phosphor becomes no more negligible. For the higher performance and longer lifetime, we have to consider phosphor layer as the heat generator and design the layer with sufficient thermal paths. (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

In this study, an improved scattered photon extraction (SPE) package structure with a reflection plate over the remote phosphor layer is presented. The important factors for the remote phosphor layer in the conventional and improved SPE package structures, including the phosphor layer thickness and phosphor concentration, are also studied. The simulation results show that the yellow-blue ratio (YBR) of the conventional and improved SPE package structure increases with the phosphor concentration when the phosphor layer is thin and that the YBR is saturated when the layer is thick. The experimental results show that for both conventional and improved SPE package structure, the correlated color temperature (CCT) decreases as the phosphor concentration increases. However, the YBR of the improved SPE package structure is higher than that of the conventional SPE package structure for a given phosphor layer thickness and phosphor concentration. That is, in the conventional SPE package structure, it is necessary to increase the phosphor concentration and then increase the absorption of blue light to obtain more yellow light. Hence, for the improved SPE package structure, less phosphor is required in the phosphor layer for achieving the chosen CCT.

ZrO2/epoxy nanocomposite for LED encapsulation

In recent years, with the development of electronic integration technology, high-speed railway transportation, new energy development, smart grid, smart furniture and other emerging industries, higher requirements have been put forward for intelligent power modules, and improvement measures have been proposed. This article will delve into the thermal management optimization of a small out-line package (SOP) typed integrated power module (IPM) packaging structure through simulation. Four optimization schemes are used to analyze the feasible conditions for improving the heat dissipation of the IPM packaging structure. They are separately from the point of view as the peripheral packaging structure, the internal layout, the internal three-dimensional stack structure and double copper substrates. It can be found that in the last scheme, the maximum temperature of the IPM packaging structure can be effectively reduced.

We present the novel 3D wafer-level vacuum packaging technology for MEMS, which only needs two masks and is realized by Au-Si eutectic bonding with a low-resistivity Si Cap wafer. Wherein, Au-Si bonding pads and rings are formed to accomplish vertical interconnects and a vacuum package respectively. Applied to resonators with two typical substrate wafers of Si and Glass, this 3D package structure has further gone through the systemic characterizations. Specifically, the high-reliable mechanic strengths of device packages are revealed from Au-Si bonding strengths measured as about 20 MPa in tensile tests. Based on analyzing parasitic capacitance networks in device packages, the feed-through effect in resonance tests can be effectively relieved by grounding on each Si layer in device package structures (i.e. the parasitic capacitance reduced from the level of pF to fF). By resonance tests, it is found that increasing the degassing duration (30 min <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 60$ </tex-math></inline-formula> min <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 100$ </tex-math></inline-formula> min) is beneficial for improving package vacuum degrees as well as consistencies (69% within 4–30 kPa <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 88$ </tex-math></inline-formula> % within 0.6-1.2 kPa <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 85$ </tex-math></inline-formula> % within 0.6-0.8 kPa), and hermetic package yields (73% <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 86$ </tex-math></inline-formula> % <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\to 100$ </tex-math></inline-formula> %). Besides, device packages are verified to have good long-term stability by monitoring quality factor variations in 6 months. Overall, this proposed 3D packaging technology has extensive application prospects in various MEMS devices due to its inherently-simple process, low capacitive feed-through effect, and fine package performances. Also, test results provide instructions on the realization of low-parasitic-capacitance signal interfaces and the optimization of wafer-level vacuum package processes.

This study presents a structure design and process method for lens type LED package. Dome type or side-emitting-enhancement silicone lens without molding process are achieved. The ceramic ring is adopted as the confine for the encapsulant. The surface intension along the sidewall of ceramic ring and silicone surface, the cohesion force and the gravity of silicone determine the shape of dome type silicone lens. The cone shape tooling coated with a releasing material is immersed into the dome type silicone lens before the silicone fully hardening. After curing simultaneously, to remove the tooling from package, the package with side-emitting-enhancement silicone lens is finished. With the mentioned architecture and process, this LED package herein has three merits, (1) to improve light extraction efficiency: reduce the chance of total internal reflection by the geometry of dome type silicone lens. (2)To enhance the flexibility of LED package design, the die placement location would be constrained by the mold in the traditional package process. (3) Mold-less side-emitting-enhancement silicone lens. Furthermore, two types of cone shape tooling are implemented and compared for side-emitting-enhancement silicone lens. Measurement results show the ratio between the lens high and lens radius could achieve 0.9:1. The view angles of dome type and side-emitting-enhancement LED packaged devices can reach 153° and 180 °, respectively. As using the same brightness grade of LED chip, the luminous flux is increasing 15% as compared the dome type package with the commercial PLCC (Plastic Leaded Chip Carrier) type package. The luminous flux of side-emitting-enhancement LED package decreases 8% as compared with the dome type one.

LED is the revolution in the illumination industry due to its great performance of solid state lighting, environment friendly working, power saving and long lasting life. But dissipation of heat generated and subsequently the thermal management in the LED package is a challenge. A steady state thermal analysis of a typical high power LED model with power dissipation values ranging from 1– 3W, consisting of LED chip, submount, heat slug and silicone enclosure is carried out in order to minimize the junction temperature of LED system. A three dimensional finite element model of the LED package is solved numerically and simulated using ANSYS Workbench to fulfill the purpose. Junction temperature is a critical parameter which affects the efficiency, reliability and lifetime of the LED. In order to minimize the junction temperature, a parametric study is carried out. This study consists of critical geometric parameters such as size of the die, thickness of the submount adhesive, width and thickness of lead frame and height of encapsulation as well as thermal properties of die attach, submount adhesive and encapsulation covering most common adhesive, die attach and encapsulant materials. Recommendations are provided regarding both geometric and process parameters to minimize the junction temperature which will improve the overall reliability and performance of the LED package.

With the emergence of three-dimensional integrated circuits, the integration of chips has been rapidly improved. The volume is significantly smaller and the power consumption is significantly reduced, but the thermal effect problem is becoming more and more prominent. In a high-density integrated module, multiple heat sources will enhance the thermal coupling effect and generate high heat flux density points, resulting in component performance degradation or even failure. Therefore, in order to promote the development of 3D chip integration technology, it is necessary to master more optimized pre-package thermal design methods, and high-precision package thermal simulation and thermal test verification technology has become a key technology that must be broken through in the field of integrated circuit thermal management optimization. In this paper, for the three-dimensional stacked packaging structure, the thermal test verification chip has been designed and fabricated. The high-precision thermal resistance test and thermal simulation analysis technology research will be carried out. Hot-spot electrical transient thermal test technology realizes high-precision multi-heat source stacked package thermal resistance test verification at the design stage. The multi-heat source stacked package structure consists of thermal test verification chips and memory chips. Then by importing the thermal resistance test structure function into Flotherm software, the finite element simulation model is fitted and calibrated, and a thermal simulation model equivalent to the actual product packaging structure is established. The evaluation of the heat dissipation scheme of the stacked package in the early stage of the design can be realized, which provides effective technical support for the optimization design of the package heat dissipation structure.

Junction temperature and thermal resistance are important factors in determining the overall performance of LED packages. Thermal transient measurements of multi-chip high brightness LED package with two specified positions under various ambient temperatures are discussed in this paper. Case 1 and case 2 are introduced as the inclined angle of the package at 0° and 90°. The main goal is to study the thermal characteristics of the LED package at different degree of inclinations using thermal transient tester (T3ster). Experimental results on junction temperature and thermal resistance for both cases at different ambient temperature are presented. From the obtained structure functions, results shows that the position of an LED package would influence the heat transfer of the whole LED package.

Hybrid Wafer-Level Packaging for RF-MEMS and Optoelectronic Applications