Thermal analysis of multi-chip module high power LED packaging

The optical performance and reliability of High power light emitting diode (HP-LED) devices can be affected by the junction temperature, while thermal resistance is one of the main factors which influence the p-n junction temperature, especially for the thermal spreading resistance. So, Thermal analysis was conducted by differential structure functions combining with finite element analysis and calculation of thermal spreading resistance of HP-LED devices. The results show that thermal spreading resistance plays an important role on total thermal resistance of LED devices. The thermal spreading resistance shows a declined and then increased trend with the increase of substrate thickness; the contact area between the heating source and substrate is the main factor which influences thermal spreading resistance; It is beneficial to decrease the thermal spreading resistance when contact area ratio be increased. Thermal-convection resistance becomes the main factor that influences total thermal resistance of HP-LED devices with the changing of substrate bottom area, while the influence of thermal spreading resistance is weak. The eccentric distance between chip and substrate plays a distinct impact on thermal spreading resistance and junction temperature. The results of finite element simulation are in good agreement with calculation of thermal spreading resistance.

The optical performance and reliability of High power light emitting diode (HP-LED) devices can be affected by the junction temperature, while thermal resistance is one of the main factors which influence the p-n junction temperature, especially for the thermal spreading resistance. So, Thermal analysis was conducted by differential structure functions combining with finite element analysis and calculation of thermal spreading resistance of HP-LED devices. The results show that thermal spreading resistance plays an important role on total thermal resistance of LED devices. The thermal spreading resistance shows a declined and then increased trend with the increase of substrate thickness; the contact area between the heating source and substrate is the main factor which influences thermal spreading resistance; It is beneficial to decrease the thermal spreading resistance when contact area ratio be increased. Thermal-convection resistance becomes the main factor that influences total thermal resistance of HP-LED devices with the changing of substrate bottom area, while the influence of thermal spreading resistance is weak. The eccentric distance between chip and substrate plays a distinct impact on thermal spreading resistance and junction temperature. The results of finite element simulation are in good agreement with calculation of thermal spreading resistance.

A study on the thermal resistance over solid–liquid–vapor interfaces in a finite-space by a molecular dynamics method

As a highly efficient heat dissipation unit, a micro heat pipe is widely used in high heat flux microelectronic chips, and its thermal resistance is crucial to heat transfer capacity. Through analyses of the structure and heat transfer performance of a circular heat pipe with sintered wick, the theoretical model of total thermal resistance was established on heat transfer theory, and then simplified, finally a testing platform was set up to test for total thermal resistance performance. The testing results show that when the micro heat pipe is in optimal heat transfer state, its total thermal resistance conform well with that from the theoretical model, and its actual thermal resistance is much lower than that of the rod made of the material with perfect thermal conductivity and of the same geometric size. With the increment of heat transfer capability, the total thermal resistance of a micro heat pipe with sintered wick decreases first, then increases and reaches the minimum when it is in the optimal heat transfer state. The greater total thermal resistance in low heat transfer performance is mainly caused by too much working fluid accumulating in evaporator and the lower velocity in vapor cavity, and the greater total thermal resistance in high heat transfer performance is mainly due to the working fluid drying up in condenser. Total thermal resistance is related to many factors, such as thermal conductivity of tube-shell material, wall thickness, wick thickness, copper powders grain size and porosity, the lengths of condenser and evaporator, and the diameter of vapor cavity etc.. Therefore, the structure parameters of a micro heat pipe with sintered wick should be reasonably designed according to the specific conditions to ensure its heat transfer capacity and total thermal resistance to meet the requirements.

Junction temperature and thermal resistance are important factors in determining the overall performance of LED packages. Thermal transient measurements of multi-chip high brightness LED package with two specified positions under various ambient temperatures are discussed in this paper. Case 1 and case 2 are introduced as the inclined angle of the package at 0° and 90°. The main goal is to study the thermal characteristics of the LED package at different degree of inclinations using thermal transient tester (T3ster). Experimental results on junction temperature and thermal resistance for both cases at different ambient temperature are presented. From the obtained structure functions, results shows that the position of an LED package would influence the heat transfer of the whole LED package.

The accurate measurement of the thermal contact resistance between multilayers within press pack insulated gate bipolar transistors (PP IGBTs) is significant for optimizing their thermal resistance to improve reliability, as thermal contact resistance accounts for about 50% of their total thermal resistance under the rated clamping force. The components within PP IGBTs are very small, and an external clamping force is needed to ensure they work normally. Thus, the methods of thermal contact resistance measurement of steady-state and transient methods are no longer suitable. In this paper, the method of thermal structure function is proposed to measure the thermal contact resistance between multilayers within PP IGBTs. The accurate measurement of the transient thermal impedance curve of PP IGBTs is the key to this method, and it can then be transformed to a cumulative and differential structure function to determine the thermal contact resistance accurately. A single fast recovery diode chip submodule is fabricated to predict the thermal contact resistance behavior within PP IGBTs in this experiment, and the experimental results agree well with theoretical values. Furthermore, the influence of both the high temperature and the clamping force on the thermal contact resistance can also be obtained from this method accurately.

The junction temperature of LEDs is important for its life, reliability and efficacy. The thermal resistance measurement can be implemented to obtain the junction temperature of a single-chip LED in different power consumptions and different environment temperatures. However, for the multichip applications such as Chip-on-Board (COB), multi-color and high-voltage LED packaging etc., only the average junction temperature can be obtained by the traditional steady thermal resistance measurement. In this paper, a thermal resistance matrix with thermal coupling factor is proposed to obtain the junction temperature of each chip in a multi-chip LED with different chip powers. In the case study, each element of the 4×4 thermal resistance matrix of a Red-Green-Blue-White (RGBW) four-chip LED is tested by a transient thermal tester (T3ster) to investigate the thermal coupling of chips one another. In addition, the thermal distribution of the LED package was analyzed by finite element analysis (FEA) simulation for comparison. It is shown that the thermal resistance matrix is effective for evaluation of junction temperature of each chip in the multi-chip LED package with a discrepancy less than 2.5% from measurement.

With the increase of power consumption and running speed, the junction temperature of three-dimensional stacked memory devices has increased. It eventually leads to chip overheating and may cause device failures. It is essential to analyze and optimize the thermal performance of the package. In this paper, the finite element analysis method is used to study the influence of the package module on the chip junction temperature and thermal resistance for the typical six-layer stacked memory chip packaging structure. The main influencing factors are investigated. In addition, the thermal characteristics of the stacked packaging structure are optimized by using the orthogonal experimental design method. After further optimization, the junction temperature decreases by 7.17% and the thermal resistance decreases by 11.59%.

PurposeThe purpose of this paper is to optimize the configuration sizes of micro‐channel cooling heat sink using the thermal resistance network model. The optimized micro‐channel heat sink is simulated by computational fluid dynamics method, and the total thermal resistance is calculated to compare with that of thermal resistance network model.Design/methodology/approachTaking the thermal resistance and the pressure drop as goal functions, a multi‐objective optimization model was proposed for the micro‐channel cooling heat sink based on the thermal resistance net work model. The Sequential Quadratic Programming procedure was used to do the optimization design of the structure size of the micro‐channel. The optimized micro‐channel heat sink was numerically simulated by computational fluid dynamics (CFD) software.FindingsFor the heat sink to cool a chip with the sizes of L × W = 2.5 mm × 2.5 mm and the power of 8 W, the optimized width and height of the micro‐channel are 154 μm and 1,000 μm, respectively, and its corresponding total thermal resistance is 8.255 K/W. According to the simulation results, the total thermal resistance of whole micro‐channel heat sink Rtotal is 7.596 K/W, which agrees well with the analysis result of thermal resistance network model.Research limitations/implicationsThe convection heat transfer coefficient is calculated approximatively here for convenience, and that may induce some errors. Originality/value –The maximum difference in temperature of the optimized micro‐channel cooling heat sink is 59.064 K, which may satisfy the requirement for removal of high heat flux in new‐generation chips.

The microelectronic chip thermoelectric cooling equipment and its test system have been developed for the deficiency of the conventional cooling technologies in this paper. The thermal resistance analysis model was applied in research the heat transfer process of the microelectronic chip cooling system and its characteristics. The results show that: When the thermoelectric cooling (TEC) system is in normal operating condition,the Peltier effect is the dominant role in the thermoelectric cooling process despite the opposite actions of the Joule and Fourier effects. The thermal resistance of TEC, which is Q2, decreases when the operating current (I) increases. For the different chip power, there is an optimum current (Iopt) making the interface thermal resistance between chip and TEC minimum (Q1). Q1can obtain the minimum 0.465°C·W-1 when the chip power is 25W and Iopt is 2.4A. The total thermal resistance (Qtotal) firstly decreases and then increases with the increase of operating current. There is an optimum current which allows the total thermal resistance is smallest. Qtotal may obtain the minimum value 0.672°C·W-1 when the chip power is 25W and Iopt is 2.4A. Furthermore, Qtotal Iopt both increase by the chip power.

The electrical performance and the long-term reliability of GaN-based high electron mobility transistors (HEMTs) are greatly affected by the Joule self-heating effect under high power density operation condition. Measurement of the junction temperature and analysis of the thermal resistance of the constituent layers including the packaging material are critically important for thermal design and reliability assessment of GaN-based HEMTs. In this paper, Raman thermometry combined with the finite element thermal simulation is used to compare the junction temperature and the thermal resistance of a GaN HEMT mounted on a novel Cu/graphite composite flange with those of a conventional CuMo flanged device. The results show that the junction temperature of the Cu/graphite flanged device is 15% lower than that of the CuMo flanged device at a power dissipation of 1.43 W/mm, while the overall device thermal resistance is 18.7% lower in the Cu/graphite flanged device. In addition, the temperature distributions of each layer along the cross-plane direction are analyzed for the two devices; the thermal resistance ratio of the Cu/graphite flange is 40% of the overall device thermal resistance, while the CuMo flange account for 53% of the overall thermal resistance of the device. This proves the effectiveness and benefit of using the Cu/graphite composite material package of high thermal conductivity to improve the heat dissipation of GaN HEMTs. By tuning the mass fraction of the graphite, it is possible to further increase the thermal conductivity of the Cu/graphite composite flange and to further reduce the device thermal resistance. It is observed in the Raman thermal measurement that the highest thermal resistance after flanging is the interfacial thermal resistance between the GaN epitaxial layer and the SiC substrate (~50 m<sup>2</sup>·K/GW). For obtaining the better thermal characteristics of the GaN HEMT, it is crucial to reduce the GaN/SiC interfacial thermal resistance through interface engineering during the epitaxial growth. In the meantime, Raman thermometry combined with the finite element thermal simulation is demonstrated to be an effective method for implementing the thermal characterization of the GaN-based devices and the constituent material layers, and the principle and procedure of the method are described in detail in the paper.

In this paper, thermal impedances of Silicon carbide (SiC) power module assembled with a Schottky Barrier Diode (SBD)–wall–integrated trench MOSFET (SWITCH–MOS) and a conventional trench gate MOSFET (UMOS) are measured. Then they are compared to show the advantage of SWITCH–MOS for thermal impedance measurement. SiC power device is attracting attention as a candidate for future power device, since it can be operated at higher current density and higher switching speed than conventional silicon (Si) power device. The power module packaging technology for SiC power device should have low thermal impedance (both transient and steady state thermal resistance) to bring out a potential ability of the device. Thermal design often has difference from measurement due to various modeling errors such as power device heat generation, module structure, interfacial thermal resistance, and cooling environment. Therefore, accurate thermal impedance measurement is an essential technology. However, the thermal impedance measurement of SiC power modules has the significant issue due to the instability of the body diode built into the SiC–MOSFET. The thermal impedance is the junction temperature rise per heat generation amount of the device. The temperature dependence of the knee voltage of the body diode is used to measure the junction temperature of the MOSFET. Since the knee voltage of SiC–MOSFET changes depending on the gate voltage, a high negative gate bias was necessary to avoid this effect. However, the negative gate bias stress may cause serious device damage such as threshold shift. The SWITCH–MOS which has SBD built in near the MOSFET channel is expected to stabilize the junction temperature measurement and avoid the risk of device deterioration. Figure 1 shows the cross–sectional schematic of the SWITCH–MOS and the conventional UMOS. The SBD are formed on the trench sidewall in SWITCH-MOS, and the device structure is almost same to the UMOS. The temperature is detected by the PiN diode for the UMOS and by the SBD for the SWITCH–MOS. Both of them measure the temperature inside of the MOSFET cell. The appearance of the test module is shown in Fig. 2. Each type of the test module is composed of the SiC die (SWITCH–MOS, UMOS, and SBD), an SiN–AMC insulating circuit substrate and an Al baseplate. The components are attached each other using AuGe solder. The junction temperature is measured from the built–in voltage of the body diode in response to a constant current flowing from the source to the drain. In the case of the UMOS, the gate bias of −18 V is applied. The gate bias is zero for the SWITCH–MOS. The thermal impedance of each test module was measured by static mode (Fig. 3). Then, the thermal structure function was calculated by transient thermal analysis (Fig. 4). Both the thermal impedance and the structure function for the SWITCH–MOS and UMOS were in good agreement. Since the SWITCH–MOS does not need negative gate bias, the threshold shift issue does not occur in principle. In addition, it is possible to perform a transient thermal testing with a large current for a long time. Because the forward degradation does not occur even if a large current is applied to the SBD in the SWITCH–MOS. The SBD built into the SWITCH–MOS makes it easier and more accurate to measure the junction temperature of the SiC–MOSFET. The thermal impedance measurement using SWITCH-MOS not only allows the precise thermal modeling of SiC power modules to be performed, but also has the potential to be applied to the calibration of the thermal design and the evaluation of thermal properties inside of the package structure. Figure 1

The thermal boundary resistance is the key feature of innovative approach of high-thermal-conductivity diamond substrate for high-power GaN HEMTs, and has significant impact on the thermal design of GaN chip. A three-dimensional thermal simulation for analysis of the heat dissipation capability of different thermal designs is presented by finite element method. The model accounts for the nonlinear thermal conductivity of GaN and diamond materials by employing Kirchhoff's transformation with the aims to improve calculation accuracy. We investigate impact rules of thermal boundary resistance on the thermal design of the GaN chip, including the GaN buffer, diamond substrate, gate-gate pitch spacing, and chip size. Those results indicate that the impacts of diamond thickness and chip size on junction temperature are have a rule, the thermal boundary resistance has no influence upon the rules, but it influences the variation of the junction temperature. In addition, the rule for impact of gate-gate pitch spacing on junction temperature is limited by the thermal boundary resistance, and the impact is proportional to the value of thermal boundary resistance. What is worth our special attention is the impact of GaN thickness on junction temperature, the optimal GaN thickness should exist for the junction temperature, and is also affected by the thermal boundary resistance. Overall, we provide thermal structure design guidelines for GaN-based diamond substrate.

In this paper, Cu/SnAg double-layered bumps structure was proposed and investigated for the fine pitch flip chip applications. Test chip was designed considering the recent high speed memory device and its pad size and pitch was 60/spl mu/m and 100/spl mu/m, respectively. Cu and SnAg bumps were fabricated as a 60/spl mu/m and 20/spl mu/m thickness on SiO/sub 2//Ti/TiN/Al/TiW/Cu on Si wafer using the electroplating method. Test chip was flip chip assembled with PCB substrates using thermo-compression bonding method. Because the pitch was very tight, the flip chip bonding of Cu/SnAg double bumps was very difficult and it affected several bonding parameters such as bonding pressure, temperature, time, Cu bump diameter and so on. The bonding results were evaluated through the cross-sectional image of interconnection and the electrical continuity test of daisy chain and bump resistance using 4-point Kelvin structure. The long time reliability tests like thermal cycling test and 85/spl deg/C/85% test are now in progress after flip chip bonding and underfill dispensing.

In this paper, the effects of eutectic voids in bonding area on the thermal resistance and light output power of flip-chip ultraviolet light-emitting diode (UV-LED) devices have been studied by experiments in detail. It has been demonstrated that the eutectic voids effectively influenced the thermal resistance, the junction temperature, and the light output power of the UV-LEDs. The UV-LEDs with lower eutectic voidage exhibited a superior thermal performance based on the thermal resistance analysis. The thermal resistance was greatly reduced by 48% and the junction temperature by 3.5 °C as the driving current was 800 mA when the eutectic voidage decreased from 30% to 3%. As a consequence, a maximal enhancement of 13.3% of light output power was obtained when the LED was driven by a current of 1500 mA. These results confirmed that a better performance of eutectic flip-chip UV-LED can be obtained with lower eutectic voidage for the reason that the thermal resistance and junction temperature can be decreased effectively.