Thermal characteristics analysis and optimization of 3D-Stacked Memory Packaging

Unbalanced currents effect on the thermal characteristic and reliability of parallel connected power switches

Based on the forward voltage measurement principle, a test device was designed for junction temperature measurement. The voltage temperature coefficient is-1.49mV/°C according to the experimental data, and a series of junction temperatures were obtained on various ambient temperature. A numerical model was built by using the CFD software Flent, which was verified with the experimental data. The influence of the different structure parameters of the heat sink on heat dissipation performance was studied numerically. The results show that the optimal structure parameters were as following: Fin number is within 8~12. Fin height is within 170mm~190mm. Fin length is within 35mm~55mm. Fin thickness is within 1mm~3mm. Bases radius is within 33mm~40mm. With the chip junction temperature and the radiator weight as optimizing object, the optimal parameters were obtained as following: Fin number is 12. Fin height is 190mm. Fin length is 55mm. Fin thickness is 1.5mm. Bases radius is 33 mm.

The demand of the high storage memory is providing a momentum for stacking technology in DRAM industry. As the stack technology is developed, more heat sources are embedded in the same package footprint and increase the device temperature. Therefore, the thermal management is one of most important issues in DRAM stack package. Since the chip stack and package stack technology are competing each other as a solution of DRAM stack, it is necessary to characterize thermal behavior of each package for better thermal management. Hence, in this paper, the authors studied the thermal performance characteristics of chip stack and package stack package in component and module level. The study is focused on the dual stack, which is most demanded stack height in DRAM market. The test package and module was assembled with the thermal test die and the DRAM junction temperature was measured to compare the thermal performance. The package stack package showed better thermal performance in component level because of its larger package size. On the other hand, the chip stack package showed better thermal performance in module level when the heat sink is used.

In recent years, the studies of thermal characteristics have gained importance since it is directly related to clothing comfort. One of the ways of achieving clothing comfort is through moisture management of textiles. Moisture management refers to the controlled movement of water vapor and perspiration from the surface of the skin to the atmosphere through the fabric. The aim of this research is to study the thermal comfort characteristics of selected knitted fabrics by analyzing the thermal behavior of moisture management finished (MMF) fabrics, in order to find the suitability of the product for different climatic conditions. The knitted fabrics made from yarns of micro-denier polyester filament, spun polyester, polyester/cotton, filament polyester, and 100% cotton were used for the study. Thermal characteristics such as thermal conductivity, thermal resistance, thermal absorptivity, relative water vapor permeability, and water vapor resistance were analyzed for the MMF fabrics. The test results indicated that the knitted fabrics produced from different nature of yarns have greater influence on thermal characteristics, when they were converted into fabrics. The MMF treatment have significant effect on thermal behavior of micro-denier polyester knitted fabrics with respect to thermal conductivity, thermal absorptivity, water vapor permeability, and water vapor resistance. Among the five fabrics, it was observed that micro-denier polyester fabrics gives faster heat transfer, quicker evaporation of sweat from the skin through the fabric, and also cooler feeling at initial touch.

Three-dimensional finite-element modeling is used to determine the thermally optimum design of a GaN-on-SiC MMIC power amplifier, with a focus on the parametric influence of the thermal boundary resistance (TBR), epitaxial geometry, and dissipated linear power on the HEMT junction temperature rise. A commercial MMIC power amplifier is used to set the baseline geometry and dimensions. It is found that the frequently neglected Thermal Boundary Resistance (TBR), between the GaN and SiC, not only has a significant influence on the maximum junction temperature, but directly influences the thermally-optimal GaN thickness for the HEMT transistor. The thermally-optimal GaN thickness is a balance between spreading, vertical thermal resistance, and the magnitude of the TBR. As a consequence, it is seen the commonly used, submicron l GaN thicknesses approach optimality only when the TBR values are below 10 m2-K/GW. Additionally, it is observed that increasing the gate pitch and substrate thickness helps to diffuse the flow of heat within the substrate before it proceeds into the cooling solution, resulting in an overall decrease in thermal resistance. The numerical results are used to verify the accuracy of an available analytical solution for a surface heat source on an orthotropic multi-layer structure, albeit with assumed temperature-invariant properties, thus enabling use of this relation in scoping and preliminary design calculations.

Electronic devices produce heat as a byproduct of normal operation. Besides the damage that excess heat can cause, it also increases the movement of free electrons in a semiconductor, which can cause an increase in signal noise. The primary focus of this book is to examine various ways to reduce the temperature of a semiconductor, or group of semiconductors. If we do not allow the heat to dissipate, the device junction temperature will exceed the maximum safe operating temperature specified by the manufacturer. When a device exceeds the specified temperature, semiconductor performance, life, and reliability are tremendously reduced, as shown in Figure 1.1. Researchers estimate that every 10°C increase in junction temperature reduces the semiconductor life by 50%. The basic objective, then, is to hold the junction temperature below the maximum temperature specified by the semiconductor manufacturer.

The optimal gate delay time control between the two internal devices to achieve excellent electrical and thermal performance of the Si/SiC hybrid switch is considerably affected by several factors and requires careful adjustment to suit the different operation conditions of power converters. However, the conventional gate control solution for the hybrid switch applies a fixed delay time to achieve the minimum switching loss at a specific load current, resulting in disparities in junction temperature of internal devices over a wide load range. This effectively reduces the safe operating area by risking one internal switch subjected to overrated junction temperature in a wide range operation with regard to power handling condition. To avoid such a serious risk of reliability degradation or thermal breakdown, a novel active gate delay time control strategy based on the electro-thermal coupling loss model is proposed. The gate delay time was dynamically adjusted and optimized according to the operation conditions of power converters so that the operation junction temperature difference of the two internal devices can be minimized. Experimental results demonstrate that the junction temperature of the hybrid switch decreases by 20 °C at 8-kW load condition and its maximum power handling capability increases by 18%, without compromising the power converter's efficiency in a 20 kHz Si/SiC hybrid switch-based dc/dc buck converter compared with the conventional approach.

Characterizing semiconductor devices is often limited by temperature rises within the device under test. These junction temperature rises are a result of the static DC biasing which must be applied to the device before making characterization measurements. Junction temperature increases can distort the measurements or damage the device being tested. This paper describes a technique to characterize semiconductor devices using "bias pulses". When these pulses are properly applied to a semiconductor device, the thermal response of its junction is minimized. In other words, the device's junction temperature remains near the ambient temperature of the devices external environment, even though power is being dissipated in its junction.

Thermal management of multi-chip module high power LED (MCM-LED) packaging is one key technology to the development of the reliable MCM-LED. In this paper, referring to MCM technology applied in IC packaging, and aiming at high power flip chip GaN-based LED packaging, the thermal analysis of MCM-LED is studied. Firstly, both a 2×2 flip chip LED array that is mounted on a bracket and heat dissipation packaging structure with the performance parameters of related materials are designed. Secondly, based on principle of heat transfer, the thermal resistance network of MCM-LED heat dissipation system is expressed, and the thermal resistance of cooling channel is theoretically calculated. The total thermal resistance and the junction temperature of LED chip of theoretical value are about 6.53 K/W and 77.2°C respectively. Thirdly, based on numerical analysis method, a 3-D finite element model (FEM) is developed. The temperature distribution in the chips and packages are shown, and junction temperature and total thermal resistance of simulative value are 82.12°Cand 7.14 K/W respectively. Finally, by means of orthogonal design of experiments, the optimized prototype structure and its related parameters are concluded. Aiming at the related material and structure parameters of MCM-LED packaging, the diameter of bump is the most important factor to thermal performance, following by the bonding layer material, chip size, the thickness of bonding layer and chip spacing.

This paper presents an electro-thermal simulation model to estimate the power devices junction temperatures of traction inverter. The model includes four sub-systems: hybrid electric vehicle simulation, model of traction motor, temperature dependent power loss model, and the thermal model of traction inverter. Firstly, load profile of the traction inverter is obtained considering the vehicle dynamic, the traction motor, and the drive cycle of the vehicle. Then, instantaneous power loss is calculated by using the load profile of the inverter. Based on the power loss and developed thermal models, junction temperatures of power devices are estimated. With the feedback of the junction temperatures into the power loss model, the temperature dependent power losses are obtained. Therefore, the electro-thermal simulation of traction inverter can be conducted. The electro-thermal model presented in this paper is simulated for the Urban Dynamometer Driving Schedule (UDDS) drive cycle, and the junction temperatures of power devices are obtained.

Junction temperature (T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf> ) and forward voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> ) of LED devices are two critical LED variables that are not easily obtained in an LED system. While T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf> affects reliability and lifetime, V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> affects the power for a given current. This paper includes the modeling of T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf> and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> based on externally measurable parameters such as heatsink temperature (Ths) and LED forward current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> ). Based on the I–V electrical characteristics, the modeling of T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf> is related to the forward current and does not need the information of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> . The modeling of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> is associated with forward current and heat sink temperature instead of junction temperature. Designers can therefore estimate the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> by measuring the forward current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> and T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">hs</inf> , thus avoid the inconvenience of measurement of junction temperature. The established theoretical models for T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf> and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> are verified by testing several kinds of LEDs. Very good agreements between the theoretical and practical results have been obtained.

Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via

Junction temperature is a critical parameter for ensuring the safety and field reliability of power devices in operational dc–dc converters. Traditional electrothermal methods, which rely on iterative calculations coupling electrical and thermal models, face challenges due to the disparity in timescales, where power devices manifest dynamic operation on fast timescales, while thermal effects evolve over much longer timescales. To tackle this challenge, the article introduces a novel multitimescale electrothermal coupling model, which balances computational demand and accuracy in calculating the junction temperature of power devices under various operating conditions such as switching frequency, load profiles, and ambient temperature. The proposed model integrates a circuit model encompassing a power loss model and a state model for the power device, with a thermal model constructed using the finite element method. For reducing computational complexity, the proper orthogonal decomposition (POD) method is applied to the thermal model. The junction temperature is iteratively calculated using the multitimescale electrothermal model of the power device, which is validated in an LLC resonant dc–dc converter, demonstrating that the proposed method achieves high computational speed and accuracy. The results confirm that the multitimescale electrothermal model exhibits excellent performance in managing the complex thermal dynamics of power devices under real-world operating conditions.

The measurement of the junction temperature of power semiconductor devices during operation is highly relevant for efficient power electronic applications. This paper presents a novel galvanic isolated sensing approach for the online junction temperature measurement of a silicon carbide (SiC) mosfet. It is based on the temperature-dependent changes in the spectrum of the light emission from the body diode of the SiC mosfet. The spectrum exhibits two characteristic peaks at roughly 380 nm and around 480 nm. The first peak's intensity increases with rising temperature, whereas the other decreases. Consequently, the junction temperature can be derived from the ratio of the filtered intensities of those two wavelength regions. The proposed method is studied on the basis of a virtual experiment and experimentally validated by means of static characterization and dynamic double pulse measurement.

An increasing share of fluctuating and intermittent renewable energy sources can cause over-currents (OCs) in the power system. The heat generated during OCs increases the junction temperature of semiconductor devices and could even lead to thermal runaway if thermal limits are reached. In order to keep the junction temperature within the thermal limit of the semiconductor, the power module structure with heat-absorbing material below the chip is investigated through COMSOL Multiphysics simulations. The upper limits of the junction temperature for Silicon (Si) and Silicon Carbide (SiC) are assumed to be 175 and 250 ∘C, respectively. The heat-absorbing materials considered for analysis are a copper block and a copper block with phase change materials (PCMs). Two times, three times, and four times of OCs would be discussed for durations of a few hundred milliseconds and seconds. This article also discusses the thermal performance of a copper block and a copper block with PCMs. PCMs used for Si and SiC are LM108 and Lithium, respectively. It is concluded that the copper block just below the semiconductor chip would enable OC capability in Si and SiC devices and would be more convenient to manufacture as compared to the copper block with PCM.