Development of silicon wafer packaging technology for deep UV LED

Three-dimensional integration is considered as one of the effective methods that continue the rapid development of microelectronic technology for More than Moore. Through Silicon Via (TSV), which is used to connect signals on different layers, is the critical factor of three-dimensional integration technology. Because of its lower thermal resistance, TSV is also beneficial for heat dissipation. In order to verify the feasibility of using TSV as an internal nested heat dissipation structure in three-dimensional systems, an analytical model of internal heat transfer of a power chip with TSV was proposed. Based on the proposed theoretical model, the thermal resistance of the vertical silicon path and the TSV path is 32.4K/W and 5.34K/W, respectively. It is proved to be feasible that using TSV for internal heat dissipation of a power chip. The simulated results of the thermal resistance on the two paths are nearly consistent with the theoretical ones. So, the analytical model of the heat transfer is correct and validated.

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs. TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.

3D technology is envisioned to offer advanced integration capabilities, enabling heterogeneous system integration and offering improved performance and reduced power consumption thanks the so-called Through Silicon Vias (TSVs). Nevertheless, 3D integration is facing strong thermal issues due to its higher power density and reduced heat dissipation properties. In previous studies, it has been often reported the use of TSV insertion techniques for thermal mitigation in 3D stacked circuits. However, due to the thin oxide layer isolating TSVs from silicon substrate, the expected thermal mitigation is actually not effective for the current TSV technologies. This paper firstly provides an analytical study to project the potential benefits and drawbacks of using TSVs for thermal mitigation. Detailed FEM simulations and experimental silicon data from a dedicated thermal test chip are then used to confirm the projections and demonstrate that TSVs may even increase the temperature of hotspots. This paper secondly reports the study of the thermal performance of multiple TSV arrays using thermal simulations for various system-level configurations, including a WideIO compatible 3D circuit. Similar results are obtained where, besides not alleviating thermal issues, TSVs may produce exacerbated hotspots. The results presented in this paper indicate that the use of additional area costly TSVs for thermal mitigation is not worthy.

3D IC technologies are now approaching the innovation and business activities of semiconductor industries. 3D IC can be heterogeneous from different chip, interposer or substrate to integrate into a single package by using through silicon via (TSV) technique. With increasing functionality and performance at minimum cost and power dissipation, wide I/O memory VLSI technologies are being aggressively scaled to meet this demand. Stack memory chips using TSV technique will lead to increase a significant manufacturing challenge for semiconductor industries. TSV formation and interconnected reliability on the intermetallic compound (IMC) between the metal-metal bounded micro-bumps are crucial for 3D IC technologies. As the number and power of IC increases, lots of heat will be generated and, in turn raises the junction temperature. This will greatly deteriorate the performance of IC. Heat dissipation for 3D IC, when the power density exceeds 100W/cm2, is an important design concern before marketing. In this paper, high density TSV formed by an ultrafast pico-second laser to evaluate the behavior between manufacturing process and silicon material is presented. In addition, thermal management using finite element analysis to predict the reliability of TSV model is demonstrated.

TSV (Through-Silicon Via) 3D packaging technology has been and continues to be investigated by many of the semiconductor manufacturer and research institute as a practical way to achieve higher performance and smaller form factors. Compared with conventional 2D packaging, this can increase packing density and reduce power consumption dramatically because of shorter interconnection by vertical directional stacking. So far 3D stacking technology based on W2W bonding has developed widely such as 3D Image sensor and 3D stacking memory because it has the advantage of easier alignment and higher throughput compared with chip-to-chip bonding. However, the wafer level 3D stacking method can be only applicable to products with high production yield because overall yield of 3D stacking chips depends on the yield of multiple stacked layers. In this paper, we suggested wafer level build-up stacking process using oxide bonding and molten metal filling newly, which temporary bonding process is unnecessary and demonstrated it through experiments. Thermal stress analysis was carried out to compare the structural reliability between conventional TSV and the proposed TSV model. The simulation results indicate that the proposed TSV model is more reliable than the conventional model with respect to stress in the stack chip.

Owing to the fact that the requirements of the lifestyle for electronics devices has been shifted to a stage physically small and thin, a high density of chips is designed to meet the foregoing demands under the limited space. Although in plane IC packaging technology has been maturely developed, it has encountered a bottleneck which stops it from immediate progress. Therefore, it is inevitable that the 3DICs packaging becomes the major goal of technological developments in the future. Among them, through silicon via (TSV) is one of the critical techniques. Because of the complexity in the design of 3D-ICs, the interaction among packaging components is expected to affect the reliability. Consequently, this research presents the 3D-ICs packaging with two ultra-thin chip stackings to examine their mechanical reliability of TSV and SnAg microjoints under only the thermal cycling test and the accompanied effect of process-dependent thermal loading simulation combined with the introduction of temperature cycling loads. Several concerned parameters of the above-mentioned packaging framework, such as the chip thickness, TSV pitch, and TSV radius, are parametrically discussed by finite element analysis while the filled underfill materials with different Young’s modulus are taken into account, separately. The analytic results show that when the double-layered chip stacking packaging structure is applied by the thermal cycling period, a better fatigue life of SnAg microjoints could be obtained under the situation of either the thinner chip, the longer TSV pitch, or the smaller TSV radius. Finally, through the analytic assistance of a full factorial design, the geometrical effects of double-layered chip stacking packaging are performed parametrically investigations.

With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore's Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced packaging technologies, such as 3D chiplets hetero-integration and co-packaged optics (CPO), have become crucial for further improving system performance. Currently, most solutions rely on silicon-based technologies, which alleviate some challenges but still face issues such as warpage, bumps' reliability, through-silicon vias' (TSVs) and redistribution layers' (RDLs) reliability, and thermal dissipation, etc. Glass, with its superior mechanical, thermal, electrical, and optical properties, is emerging as a promising material to address these challenges, particularly with the development of femtosecond laser technology. This paper discusses the evolution of both conventional and advanced packaging technologies and outlines future directions for design, fabrication, and packaging using glass substrates and femtosecond laser processing.

Due to the increased power density and lower thermal conductivity, 3D is faced with heat dissipation and temperature problem seriously. Previous researches show that leakage power and delay are both relevant to temperature. The timing-power-temperature dependence will potentially negate the performance improvement of 3D designs. TSV (Through-Silicon-Vias) has been shown as an effective way to help heat removal, but they create routing congestions. Therefore, how to reach the trade-off between temperature, via number and delay is required to be solved. Different from previous works on TSV planning which ignored the effects of leakage power, in this paper, we integrate temperature-leakage-timing dependence into thermal via planning of 3D ICs. A weighted via insertion approach, considering both performance and heat dissipation with resource constraint, is proposed to achieve the best balance among delay, via number and temperature. Experiment results show that, with leakage power and resource constraint considered the temperature and via number required can be quite different, and weighted TSV insertion approach can improve thermal via number, by about 5.6%.

LEDs are widely used in medicine, navigation and landscape lighting. The development of high-power LED is a severe challenge to LED heat dissipation. In this review, packaging technology and packaging structure are reviewed in terms of the thermal performance of LED packaging, and related technologies that promote heat dissipation in LED packaging are introduced. The design of three components to enhance heat dissipation in LED packaging is described: substrate, lens and phosphor layer. By conducting a summary of the technology and structure of the package, the defects of LED package technology and structure are deeply investigated, and the package is prospected. This has reference value for the heat dissipation design of the LED package and helps to improve the design and manufacture of the LED package.

An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1-3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach) and for revealing them from the backside in the far back end of the line are described with detailed attention to major unit processes of etch, dielectric deposition, barrier and seed deposition, electrochemical deposition, and chemical-mechanical planarization. Unit-process advances are described in relation to the structural and functional requirements of the TSVs, and examples are given of co-optimization among the interdependent steps of the integrated sequence. Emphasis is given to copper vias of diameter 4 to 10μm with aspect ratio between 8 and 12. For both the viaformation and via-reveal sequence, it is shown how integration problems were overcome by a comprehensive approach.

Based on the one-dimensional analytical thermal model for N strata stacked chips without through-silicon via (TSV), the equivalent thermal model for TSV is presented in this paper. And then, the corresponding analytical thermal model with considering TSV is deriveed. Finally, Matlab software is used to verify and analyze the influence of TSV on the thermal management of 3D IC intergration. The analysis results indicate that the TSV can effectively improve the heat dissipation of 3D IC circuits, and the increase of TSVss pitch can raise the temperature of the 3D IC circuit.

This paper reports an improved deep ultraviolet LED (DUV-LED) packaging based on Si MEMS process technology. The Si package (Si-PKG) consists of a cavity formed by Si crystalline anisotropic wet etching and through-silicon vias (TSV) filled with electroplated Cu. The Si-PKG is hermetically sealed by laser local heating of screen-printed glass frit. This technology allows for the use of a DUV-transparent glass substrate, which has an unmatched coefficient of thermal expansion (CTE). Using a high-density array of TSV capped with AuSn solder bumps, the cooling performance of the DUV-LED has been greatly improved. As a result, an optical output of 114% (50 mW) and a volumetric light power density of 380% (14 mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ) were recorded compared with the conventional AlN-packaged device. The developed compact low-cost Si-PKG is promising for wider applications of the DUV-LED including the disinfection of the new coronaviruses.

3D microelectronics integration and wafer scale packaging promise improvements in functional density and cost compared to conventional 2D microelectronics and packaging technologies. The realization of these improvements will require further adoption of 3D volume manufacturing process technologies. These process technologies will likely include through silicon via (TSV) and die or wafer bonding with and without 3D interconnect. Low temperature direct bond technologies have a number of inherent performance and cost advantages compared to other bonding technologies. This paper describes low temperature direct oxide bond technologies with and without a scalable 3D interconnect developed by Ziptronix and cost savings, performance and applications that will be enabled by adoption of these technologies. Enabled cost savings and performance include system or network-on-chip, system in package, and TSVs. Enabled applications include backside illuminated image sensors, micron-scale pitch vertically integrated image sensor arrays, 3D system-on-chip and 3D network-on-chip.

Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-\mu \mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-\mu \mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $\mu$ -bumps with $25-\mu \mathrm{m}$ size on a $45-\mu \mathrm{m}$ pitch in the logic and $25-\mu \mathrm{m}$ size on a $55-\mu \mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-\mu \mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to integrate multiple functionalities and cost.

3D devices which contain two or more chips stacked vertically and connected by through silicon via (TSV) will be required for high performance computer (HPC) systems. However heat dissipation is a critical issue because 3D devices are difficult to cool the lower layer chips. In this paper, cooling behavior of 3D devices mounted on printed circuit board (PCB) with thermal vias area is studied. It is confirmed that cooling from substrate side is effective to cool the lower layer chips in 3D devices.