Differential and pass-transistor CMOS logic for high performance systems

This paper examines the performance of differential static CMOS circuit topologies based on partially-depleted (PD) and dual-gate SOI devices. Both device types have L/sub eff/=0.15 /spl mu/m. The top and bottom gates of the dual-gate device are self-aligned to the source/drain, and the device has a fanned-out source/drain structure with low parasitic resistance. The dual-gate device current drive and transconductance are about 2.2 times that of a partially-depleted device at the same bias. We compared three differential static CMOS topologies: (a) standard CMOS logic; (b) push-pull cascode logic (PPCL), a low power high speed static logic topology; (c) complementary pass-transistor logic (CPL), known for its efficiency for device use and popular for fast arithmetic operations. We considered three cases: (a) partially-depleted device with standard bulk-like connection where the body is tied to the supply rail; (b) partially-depleted device with floating body (FB); (c) dual gate (DG) device where the bottom gate is driven with the top gate simultaneously. Based on a methodology described previously (Tretz et al. Proc. IEEE Midwest Symp. on Circuits and Systems, pp. 179-82, 1996), performance comparison of these topologies is sufficient to establish the relative performance of almost any other differential static CMOS topology, using the generic differential CMOS static gate concept. All differential static circuits can be described as a variation of the generic differential static gate comprised of pull-up and pull-down switches, cross-coupled elements, additional resistive loads, and active paths to V/sub dd//GND.

As the size of today's high performance computers increases from hundreds, to thousands, and even tens of thousands of processors, node failures in these computers are becoming frequent events. Although checkpoint/rollback-recovery is the typical technique to tolerate such failures, it often introduces a considerable overhead. Algorithm-based fault tolerance is a very cost-effective method to incorporate fault tolerance into matrix computations. However, previous algorithm-based fault tolerance methods for matrix computations are often derived using algorithms that are seldomly used in the practice of today's high performance matrix computations and have mostly focused on platforms where failed processors produce incorrect calculations. To fill this gap, this paper extends the existing algorithm-based fault tolerance to the volatile computing platform where the failed processor stops working and applies it to scalable high performance matrix computations with two dimensional block cyclic data distribution. We show the practicality of this technique by applying it to the ScaLAPACK/PBLAS matrix-matrix multiplication kernel. Experimental results demonstrate that the proposed approach is able to survive process failures with a very low performance overhead.

Purpose — The purpose of this paper is to document in part the study that was conducted for a research project ASHRAE RP-1650, which investigates the training requirements for sustainable high-performance building (HPB) operations and maintenance (O&M). This paper documents the intent, procedures and findings of a portion of the research project, which includes a survey of O&M practices for high performance buildings in the industry. The purpose of the survey as reported in this paper was to confirm and refine the level of understanding of KSCs for operating HPBs as perceived by O&M personnel in the industry. The details of the survey and the results are presented in this paper. The survey was sent out to facility managers in the industry who are involved with the O&M of HPB systems and equipment. 221 facility managers were surveyed in this study. Design/methodology/approach — This study utilizes a concurrent mixed-method research, which considers both qualitative and quantitative responses. Findings — The study found that while most technicians were ‘moderately well' to ‘very well' trained for the configuration and components as well as the installation, repair and replacement of different high performance equipment and systems, they lacked essential knowledge to address issues such as: controls; tracking of variables; programming and operation of modulation devices implemented in high-performance systems and equipment. This finding implied a lack of ‘Systems Thinking' approach, which the study found to be pertinent and essential for the O&M of HPB systems and equipment. Originality/value — The study is utilized to identify gaps between the training requirements for O&M of HPBs identified from the literature review of the research project and the current industry practices. The identified gaps are valuable to develop learning objectives for training programs that are aimed to train personnel responsible for the O&M of HPBs.

Pass transistor logic (PTL) has been recently proposed as an alternative to standard MOS for aggressive circuit design. Even though PTL has been successful in a few hand-crafted designs, its acceptance into mainstream digital design critically depends on the availability of tools for logic and physical synthesis and optimization. The automatic synthesis of pass transistor circuits starting from BDDs has been intensively studied in the past with promising results, but back-end tools for PTL cell generation are still missing. We describe an automatic layout generator that has been designed for seamless integration in a library-free PTL design flow. The generator exploits the distinctive characteristics of pass transistor networks produced by synthesis to achieve quality of results comparable with state-of-the art commercial cell generation tools in a function of the execution time.

Conceptual modeling is drawing more attention among researchers from many organizations and different disciplines including high-performance low-power multicore systems. As the popularity and demand grow, more processing power is required by the mission critical systems. Several chip vendors have developed teraflop computing systems (like Intel 80-Core Research Chip). Even though IBM offers the Roadrunner supercomputer, NSF and other research organization are looking for more powerful petascale computer system. In a petascale computer system, thousands to millions of processing cores are expected to work together using petabytes of memory to produce the expected performance. A high performance system like Roadrunner requires a very sophisticated power management system. No wonder, such a gigantic system costs millions of dollars. Conceptual modeling offers the opportunity to conduct research on complex and expensive systems in an inexpensive way. In this work, we address some key conceptual modeling issues and discuss a methodology to develop conceptual models of petascale computer systems. Important features of this methodology include data acquisition to improve accuracy by capturing the important details about the system under consideration and (system-to-) model abstraction to make the modeling manageable without eliminating any significant characteristics of the target system. We believe our findings help develop sound conceptual models of complex high performance petascale computer systems.

Silicon photonics offers great opportunities to replace the bulky free-space systems with compact, highly integrated ones. However, dedicated optimization work is required to realize high performance systems for practical applications. This talk presents a library of optimized photonic components and a high-performance system as example.

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

In this paper, a new high-speed circuit technique called differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using a pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which eliminates the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type of ratioless circuit, and it also provides superior performance with less power dissipation and better silicon area tradeoff. The basic DCVSPG design technique, the methodology for optimization, and synthesis of the pass-gate logic tree are described. The standard cell library development taking advantage of the dual-rail outputs of DCVSPG gates is also discussed. The performance comparisons with other existing pass-gate circuit techniques [complimentary pass-transistor logic (CPL), double pass-transistor logic (DPL), and swing restored pass-transistor logic (SRPL)] are presented. For more robust design, the DCVSPG with inverter buffers is also the best choice. A Viterbi macro design using the DCVSPG circuit technique is demonstrated. The process that the design is based upon is a 0.5-/spl mu/m CMOS technology with 0.25-/spl mu/m effective channel length and five layers of metal. This macro can run up to 500 MHz at the nominal process condition. In comparison with other existing dynamic circuit techniques, the results also clearly show that the dynamic DCVSPG has the superior power-delay performance.

In this paper, a novel and highly efficient inexact Full Adder cell by exploiting two logic styles including conventional CMOS (C-COMS) and pass transistor logic (PTL) are presented. The so-called carbon nanotube field-effect transistor (CNFET) technology is used to implement circuits at the transistor level. To justify the efficiency of our design, extensive simulations are performed at the transistor level as well as application level. Transistor-level simulations which are carried out by the HSPICE 2008 tool, demonstrate at least 12% higher performance in terms of power-delay-area product (PDAP) of the proposed circuit compared to the latest designs. At the application level, by using the MATLAB tool, inexact Full Adders are employed in the structure of the ripple carry adder (RCA) that is applied in motion and edge detection algorithms. Computer simulation results confirm the appropriate quality of the output images in terms of the peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) criteria. At last, to make a compromise between hardware and application level parameters, the power-delay-area-1/PSNR product (PDAPP) and power-delay-area-1/SSIM product (PDASP) are considered as figures of merit. The proposed circuit shows remarkable improvement from the PDAPP and PDASP points of view compared to its counterparts.

Today's high performance in the industrial poultry industry would not have been possible without the focused specialization of production and the use of highly productive poultry crosses. Therefore, the organization of modern poultry farming used simultaneously with high productivity indicators leads to a decrease in natural resistance and an increase in the susceptibility of birds to various pathogens of infectious diseases transmitted aerogenically, which is accompanied by the manifestation of respiratory syndrome in birds. One of the key reasons for the development of respiratory syndrome is the circulation of pneumovirus in the herd, which is especially dangerous for meat farms, since in broiler chickens the disease proceeds in a more severe form compared to poultry crosses.Avian metapneumovirus infection causes significant economic damage to poultry farming, which consists of losses from a decrease in safety and productivity, as well as the cost of health and preventive measures.4 subtypes of MPV are officially known, although recent publications have reported of two new pneumoviruses, GuMPV and AMPV PAR-05 isolated from the seagull in North America.The diversity of pathogen subtypes and differences in virulence properties of metapneumovirus create difficulties both in the prevention of this disease and in its diagnosis.Difficulty of metapneumovirus isolation from the examined material is caused by the short period of virus persistence in the organs of birds.The most effective method of controlling avian MPVI is vaccination.

The most widely used parallel architectures in today's High Performance Computing systems utilize multi-core CPUs, many-core GPUs or Intel's MIC (Many Integrated Core). The effort of new algorithm and implementation development greatly influences the performance on these architectures, and the differences between their underlying ILP parallelism - namely SIMT (Single Instruction Multiple Thread) and SIMD (Single Instruction Multiple Data) - require different approaches. The aim of the work to be presented is to show how high performance can be achieved in solving multiple scalar- and block-tridiagonal system of equations. The Thomas algorithm is implemented on all three hardware platforms, and for the GPU we also implement a hybrid algorithm based on Parallel Cyclic Reduction and Thomas algorithm for solving scalar problem and a thread level, work-sharing based algorithm for block-tridiagonal problems. Performance comparisons and a discussion on efficiency are also included.

As the number of processors in today's high performance computers continues to grow, the mean-time-to-failure of these computers are becoming significantly shorter than the execution time of many current high performance computing applications. Although today's architectures are usually robust enough to survive node failures without suffering complete system failure, most today's high performance computing applications can not survive node failures and, therefore, whenever a node fails, have to abort themselves and restart from the beginning or a stable-storage-based checkpoint.This paper explores the use of the floating-point arithmetic coding approach to build fault survivable high performance computing applications so that they can adapt to node failures without aborting themselves. Despite the use of erasure codes over Galois field has been theoretically attempted before in diskless checkpointing, few actual implementations exist. This probably derives from concerns related to both the efficiency and the complexity of implementing such codes in high performance computing applications. In this paper, we introduce the simple but efficient floating-point arithmetic coding approach into diskless checkpointing and address the associated round-off error issue. We also implement a floating-point arithmetic version of the Reed-Solomon coding scheme into a conjugate gradient equation solver and evaluate both the performance and the numerical impact of this scheme. Experimental results demonstrate that the proposed floating-point arithmetic coding approach is able to survive a small number of simultaneous node failures with low performance overhead and little numerical impact.

The number of Earth observation satellites from China increases dramatically recently and those satellites are acquiring a large volume of imagery daily. As the main portal of image processing and distribution from those Chinese satellites, the China Centre for Resources Satellite Data and Application (CRESDA) has been working with PCI Geomatics during the last three years to solve two issues in this regard: processing the large volume of data (about 1,500 scenes or 1 TB per day) in a timely manner and generating geometrically accurate orthorectified products. After three-year research and development, a high performance system has been built and successfully delivered. The high performance system has a service oriented architecture and can be deployed to a cluster of computers that may be configured with high end computing power. The high performance is gained through, first, making image processing algorithms into parallel computing by using high performance graphic processing unit (GPU) cards and multiple cores from multiple CPUs, and, second, distributing processing tasks to a cluster of computing nodes. While achieving up to thirty (and even more) times faster in performance compared with the traditional practice, a particular methodology was developed to improve the geometric accuracy of images acquired from Chinese satellites (including HJ-1 A/B, ZY-1-02C, ZY-3, GF-1, etc.). The methodology consists of fully automatic collection of dense ground control points (GCP) from various resources and then application of those points to improve the photogrammetric model of the images. The delivered system is up running at CRESDA for pre-operational production and has been and is generating good return on investment by eliminating a great amount of manual labor and increasing more than ten times of data throughput daily with fewer operators. Future work, such as development of more performance-optimized algorithms, robust image matching methods and application workflows, is identified to improve the system in the coming years.

Recent advanced high-speed communication systems, such as optical systems, require highest reliability at lowest possible power consumption. Thus, Pass Transistor Logic (PTL) is gaining lots of interest in these communication systems due to its power saving potential compared to traditional CMOS logic. However, due to the non-conventional logic structure, its susceptibility to radiation-induced soft errors is different from CMOS circuitry. Due to the unique generation and propagation of Single Event Transients (SETs) in PTL, different approaches for PTL soft error rate (SER) estimation are required. In this paper we propose a machine learning (ML) approach for SET propagation in PTL logic. Multi-layer feed-forward neural network together with support vector classifier (SVC) are used to build the SET pulse width and pulse amplitude models. Bayesian optimization using Gaussian Processes is utilized to tune the hyperparameters of neural network. The experimental results on full adder (FA), which is the key component in many large cirucits such as ALU, and comparison with Monte Carlo (MC) spectre simulations confirm the accuracy and speed of the proposed method.

Temperature estimation and prediction are critical for online regulation of temperature and hot spots on today's high performance processors. In this paper, we present a new method, called FRETEP, to accurately estimate and predict the full-chip temperature at runtime under more practical conditions where we have inaccurate thermal model, less accurate power estimations and limited number of on-chip physical thermal sensors. FRETEP employs a number of new techniques to address this problem. First, we propose a new thermal sensor based error compensation method to correct the errors due to the inaccuracies in thermal model and power estimations. Second, we raise a new correlation based method for error compensation estimation with limited number of thermal sensors. Third, we optimize the compact modeling technique and integrate it into the error compensation process in order to perform the thermal estimation with error compensation at runtime. Last but not least, to enable accurate temperature prediction for the emerging predictive thermal management, we design a full-chip thermal prediction framework employing time series prediction method. Experimental results show FRETEP accurately estimates and predicts the full-chip thermal behavior with very low overhead introduced and compares very favorably with the Kalman filter based approach on standard SPEC benchmarks.