Digital Circuits Design Using EDA Experimental System

In modern IC design, circuit designers often need to manually operate and move data among different EDA (Electronic Design Automation) tools. If these tools were installed in separate computers, due to the license and system requirements, the design flow will be frequently interrupted, to handle the dreary data movement work, and the design efficiency will thus be reduced. To alleviate the above problem, a seamless and efficient design flow would be a must. The aim of this paper is to propose a service-oriented integrated EDA environment that can improve the smoothness of the design flow and consequently increase the overall design productivity. In our approach, a multi-agent framework based on JADE platform is used to manage distributed EDA tools, which are encapsulated as agent services. Mobile agents are allowed to autonomously and concurrently migrate among computers to access services for IC designers. To facilitate that, a scripting language is designed for mobile agents to allocate tasks, cooperate with each other, and select appropriate services. To demonstrate the feasibility of our method, an Integrated Circuit Design Cycle Assistant System (ICDCAS) for simplifying the manual operations in IC design cycles is developed by combining two EDA tools: ModelSim and Xilinx ISE. The implemented system proves to have the features of time saving and being free of mistakes incurred by manually operating and configuring the sophisticated EDA tools.

Large Language Models are having a substantial impact on electronic design automation in areas ranging from hardware architecture to verification and optimization. The special issue provides a snapshot of work on this topic. This introduction describes and provides context for the research area, describes the organization of the special issue, and provides terse summaries of each of its papers.

The low carrier mobility of (printed) semiconductors and high variations of the printed/flexible electronic elements are some of the most difficult challenges for the practical realization of complex printed/flexible electronic circuits. Although contemporary circuit designs accommodate some degree of process variations in conventional silicon processes largely by negative feedback, negative feedback is largely inapplicable in printed/flexible electronics. This is because the gain of the transistors is too low in electronic circuits to realize high open-loop gain, but also because negative feedback is inapplicable to digital circuits in the traditional sense. In this paper, we describe the co-design between the first three supply chains of Printed/Flexible Electronics – the co-design between our modified semiconductor, Fully-Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics printing process and a process-variation-tolerant digital circuit design methodology. The first two co-design supply chains pertain to a low-cost screen-printing process while the last co-design chain pertains to the Quasi-Delay-Insensitive asynchronous-logic digital design methodology (vis-a-vis synchronous-logic) that is self-timed, hence virtually tolerant to any variations. We will also delineate our measurements on digital circuit based on codesign of the aforesaid supply chains, depicting the merits of our modified semiconductor, low-variation printing process, and the ensuing functional printed digital circuit.

2 - Modern control systems design using CAD techniques

Digital Electronic Design Automation (EDA) tools have seen a remarkable improvement over the last decade. In addition to providing good documentation, their ability to simulate a design provides immense convenience in optimizing a design and in examining what-if scenarios which would otherwise be very time-consuming, expensive, and even impossible using hardware. This paper begins with an overview of EDA tools and related issues. Next, it discusses the implementation of an EDA laboratory established with funding from the National Science Foundation. Details of four experiments and an evaluation of the EDA tools used in the undergraduate curriculum have been presented.

In this paper, the authors present a rapid prototyping environment for teaching digital logic design. Their primary goal was to build an FPGA based hardware prototyping system that provides sufficient flexibility for the implementation and functional verification of various digital circuit designs. Since the system is intended to be used as an experimental and demonstration board to support digital design courses and practices for the undergraduate students, it is simple to use and completely supported by the software for automatic implementation of digital circuits. The prototyping environment consists of a PC and the programmable board composed of 3 FPGAs. One FPGA is used to implement the digital circuit, while the rest of the devices implement an interface between the digital circuit and the PC. The PC is used for designing a digital circuit, automatic generation of the interface logic, programming the FPGAs and as a test engine for functional verification of the designed circuit. The presented environment is used in the regular educational process and the sample student projects are summarized.

With Moore's law in effect, as the complexity of digital electronic circuits increases, the amount of time spent by the electronic design automation (EDA) tools to design such circuits also increases. It brings us to the point, where we need to improve the performance of EDA algorithms to fulfil the present and the future requirements of the EDA industry. Out of many algorithms used by these tools, Breadth First Traversal (BFT) is one of the most commonly used algorithms to traverse the gates of electronic circuits. In this paper, we present a new simple, fast and parallelizable BFT algorithm for sparse graphs, named H-BFT. We show that the CPU implementation of H-BFT is about 75× faster than the CPU implementation of the state of the art, the Sparse Matrix-Vector Product (SMVP) based BFT. Further, with the new features introduced by NVIDIA in their GPUs, we have accelerated both the state of the art SMVP based BFT implementation and our new H-BFT implementation. The best speedups we achieved via these accelerations are 180× and 25× for the SMVP-BFT and H-BFT respectively.

Digital integrated circuit design serves as a crucial required course for students majoring in electronic science and technology. This subject combines theoretical knowledge with practical applications, playing a key role in establishing a strong foundation for students’ academic and career growth. Guided by the OBE concept, the reform of digital integrated circuit design aims to transcend traditional limitations, explore more efficient and high-quality teaching methods, and cultivate outstanding talents according to predefined goals, enabling them to meet job market demands and adapt to industry changes. To enhance the training model for professional talents in electronic science and technology and support the long-term development and planning of students, this approach achieves multiple objectives simultaneously. Consequently, this paper explores the essence of the OBE concept and provides an in-depth analysis of the current state and potential reform directions for the digital integrated circuit design course, aiming to offer valuable insights for educators on the front lines.

A digital VLSI circuit design for an adaptive resonance theory (ART) neural network architecture, called the augmented ART-1 neural network (AARTI-NN) is presented. An ‘axon-synapse-tree’ structure is used to realize the activities of the short-term memories and reset subsystem. The long-term memory traces are implemented using NMOS transmission gales. PSpice circuit simulation was carried out to verify the design of a prototype, seven-node AARTI-NN. A clock-controlled delay element is included in the simulation to illustrate the functionality of the AARTI-NN. It is shown that the AARTI-NN node selection activities simulated from the circuit designed are identical to those described by the coupled differential equations governing the AARTI-NN.

In this paper it is proposed the implementation in Matlab & Tools environment, by using Simulink and Simscape plug-ins, of empirical models of the Carbon Nanotube Field Effect Transistor (CNTFET) in order to evaluate the capability of this very interesting design and simulation environment to easily design the most advanced generation of digital electronic circuits. Empirical models of electronic devices are particularly suitable for the Computer Aided Design (CAD) of digital electronic circuits. They are generally very compact, fast and accurate, without any physical approximation, and then they can be easily implemented in circuit simulators. The paper aims at describing the core of a possible CAD tool for digital circuits using CNTFETs, designed by the author, and at evaluating its suitability and usefulness by design examples. Therefore, they have been implemented two models of CNTFETs in Matlab & Tools environment and it has been performed the design of basic digital logic gates and memory elements. One of the two models has been developed by the author and already validated. The other model has been developed by valuable authors at Standford University and is used for comparisons. Results show the great usefulness of the empirical approach and of the Matlab & Tools environment for the quick and easy design of digital electronic circuits using CNTFETs.

Advancements in Silicon Carbide (SiC) digital integrated circuit (IC) design have enabled the ability to design complex, dense, digital blocks. Because of the large number of transistors, these complex digital designs make the time and risk of hand-crafted digital design, which has been the norm for SiC, too costly and risky. For large scale integrated digital circuits, computer aided design (CAD) tools are necessary, specifically the use of automatic synthesis, rule-based placement and signal routing software. The tools are used in progression as a design flow and are necessary for the timely and accurate creation of high-density digital designs. Application of an automated digital design flow to high-temperature SiC processes presents new challenges, such as extraction of timing characteristics at high temperatures, specifically above 400°C, as well as managing the complexity of synthesis, optimization of cell placement, verification of timing enclosure, and identifying routing constraints. These activities all require a willingness to extend and enhance the CAD software. Presented is a high temperature SiC digital synthesis flow. This flow is fully integrated with the characterization of a standard cell library that considers the variation of voltage, temperature, and process characteristics. A digital controller for a 10,000-pixel UV focal plan array (FPA) in a SiC CMOS process was designed using this high temperature digital flow. The controller is comprised of a finite state machine (FSM), that monitors several counters, shift registers and combinational logic feedback signals. The FSM is configured to optimize the FPA for different applications and exposures. The Register-Transfer Level (RTL) design of the FSM produces between 900 and 1,000 gates, depending on the temperature-dependent time closure with a total footprint of 14mm2. Typical SiC processes present a non-monotonic clock speed over temperature. The advantage of this digital design flow is that it allows the designer to target a temperature corner for the netlist design but verify its operation over a > 400°C operating range. This flow is currently being enhanced for use with NASA's SiC JFET-R process to create a high temperature communication protocol interface.

In this paper a state of the art, main problems and future trends concerning evolutionary design of combinational digital circuits are presented. Several evolutionary algorithms for design and optimization of combinational digital circuits are also shortly described. In evolutionary design methods the main problem is related to "combinatorial explosion" existing in those methods. Because evolutionary design methods are based on "generate and test" model, therefore together with growing of digital circuit input number, the number of potential combinations which must be tested are growing exponentially. This problem is a "bottle-neck" of those methods, and therefore it is discussed in details in this paper. To solve this problem it becomes important to elaborate efficient decomposition techniques of the designed circuits to some less complex sub-circuits, and then to design each of them independently. Also, it is important to create novel genetic operators (as mutation and crossover) which will always lead to acceptable solutions (solutions which satisfy the truth table). Due to such kind of operators, any repair mechanisms need not necessarily be used, and therefore the "generate and test" model will be simplified only to generation of new solutions, and therefore evolutionary design methods will become more effective.

This article describes a brief history of the development of the CAD system for integrated circuit design in Russia. The background of the beginning of the import-independent Russian CAD for digital integrated circuit design "Obsidian" is presented. What tasks were set for the developers and which results have been achieved up to the present. The results of a large set of tests obtained by "Obsidian" to compare this system with commercial CAD tools for digital integrated circuit design are presented. Further directions of the development of CAD of digital integrated circuits have been determined for separate stages of the design route.

The article presents and describes in detail the laboratory work “Digital circuit design and algebra of logic: creation of digital devices in an online simulator”, conducted for high school students at Bauman Moscow State Technical University. The introduction describes the place of the lesson in the system of interaction between organizations of secondary general and higher levels of education; based on the considered problems of education in the field of digital circuitry, the rationale for the need for this laboratory work is given. The practice-oriented nature of the considered laboratory work in informatics necessitates the use of modern modeling tools. This laboratory work uses the online environment Logic.ly, which allows you to create and explore digital devices: half-adder, adder, flip-flops, multi-plexers, decoders. The main characteristics, structure and stages of the lesson, subject content and interdisciplinary connections, target subject and meta-subject results based on a modern competency-based approach are described in detail.

As the semiconductor industry moves into the next generation sub-nanometer design the quality of the electronic design automation (EDA) tools becomes more critical. With shrinking market windows and increasing time to market constraints the designers need reliable and robust EDA software tools to ensure that the design is manufacturable with an acceptable yield. This paper develops a balanced scorecard for implementing systemic quality in an EDA organization.