Digital predistortion techniques for linearized power amplifiers

: A key component of microwave telecommunication systems is the power amplifier (PA). The design parameters of a communication system, such as link performance, power budget, and thermal design are typically driven by the power amplifier's linearity, output power, and efficiency. These design parameters of PA are the key to ensuring an efficient system because the PA is the most power-consuming circuit in the communication system. In an effort to have students involved in this research area, the International Microwave Symposium (IMS) sponsored by IEEE Microwave Theory and Technique Society (MTT-S) has introduced a High Efficiency Power Amplifier Design Competition. In this report, we present a 2.8-GHz, 5-W, highly efficient PA based on a wide bandgap gallium nitride (GaN) high electron mobility transistor (HEMT) device (CGH 40010f from CREE). The PA design was presented at the 2010 IMS Student Design Competition and achieved the competition goal of output power greater than 5 W with a measured power added efficiency (PAE) of 61% at 2.8 GHz.

Long-term-evolution (LTE) communication enables high data-rates but degrades the efficiency of the power amplifiers (PAs) due to high peak-to-average power ratios of transmitted signals. Envelope tracking (ET) and envelope-elimination-and-restoration (EER) techniques have been proposed to improve the PA efficiency by adapting the PA supply voltage to the envelope. Linear PAs in ET systems are mostly implemented in non-CMOS technologies for high efficiency [1]. However, the growing demand for low-cost integrated systems has motivated the use of CMOS PAs [2]. The main drawback of this is that linear CMOS PAs have poor efficiency. The high efficiency of switching PAs makes them a promising candidate in CMOS [3]. In EER systems, where switching PAs are used, the supply modulator must satisfy stringent noise and bandwidth specifications in order to recover the amplitude information of the LTE signal. Thus, it is a challenge for supply modulators to maintain high efficiency. Recently, a number of methods have been adopted to improve supply-modulator efficiency. In [1], a dual-switching topology is proposed, but it requires an additional inductor and results in an unpredictable noise spectrum. In [4], an AC-coupling topology is adopted to reduce the supply voltage of the linear amplifier. However, due to the slow response of the switching amplifier, the efficiency is still low.

Linear Power amplifiers become very a hot issue for the mobile communication. The main focus is high efficiency to reduce cost. The other is the flexibility to handle various services. The meet the requirements, the transmitters are assisted by digital technique. The performance of the unit PAs is improved significantly using GaN technology. The class E, J, F and saturated amplifiers are heavily researched. To improve the performance further, the unit amplifiers are utilized in transmitter architectures such as Doherty amplifier, Envelope Tracking, and class-S, which are assisted by digital circuits. These advanced architectures will be introduced. Finally, the digital predistortion technique will be discussed, which is the main linearization technique of the transmitters.

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), [Formula: see text]) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR [Formula: see text]50[Formula: see text]dBc, at 10[Formula: see text]W LTE modulated PA output, antenna point and PA output power of 39.5[Formula: see text]dBm.

This paper discusses a method for improving the efficiency of linear power amplifiers by externally injecting power into the output at the second harmonic frequency. An experimental proof-of-concept PA based on class-A/AB mode with a 10-W GaN pHEMT at 2.45GHz is presented, and its efficiency improved from 58% to 75% with −6.5 dBc injected 2nd harmonic power. Two-tone measurements confirm improved linearity with simultaneous increase in efficiency, accompanied by gain compression at higher input power.

This paper presents a compact transformer-based linear and efficient power amplifier (PA) in 0.13-μm SiGe:C BiCMOS for 5G applications. To reduce the form factor, an ultra-compact neutralized cascode PA core is proposed, which achieves a state-of-the-art power density. To obtain a gain flatness at 5G NR band n257 (26.50-29.50GHz), transformer-based input and output matching networks are designed. The PA demonstrates a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$S_{21}$</tex> 3-dB bandwidth <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(BW_{-3\text{dB}})$</tex> of 10.5GHz from 23.5 to 34GHz. At 28GHz/29GHz, the saturated output power ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{\text{sat}}$</tex> ) are 22.7/22.4dBm with power-added efficiency (PAE) of 38.1/39.8%. The PA also supports 64- and 256-QAM modulated signal tests without digital pre-distortion (DPD). Over 26-30GHz, for 4.8Gb/s 64-QAM signals with peak-to-average power ratio (PAPR) 8.3dB at −25dB EVM, this PA continuously achieves >16dBm average power ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{\text{avg}}$</tex> ) with >11% PAE.

Linear amplification using nonlinear components (LINC) is a method of vector summing two constant amplitude phase-modulated signals to achieve power amplification. The theoretical efficiency of the LINC power amplifier has been reported as 100% since highly efficient nonlinear constant amplitude amplifiers can be used. However, the 100% efficiency performance is only possible at one or two loads along the power output curve. The bulk of the papers regarding LINC has focused on clever implementations of the signal vector decomposition as well as methods to achieve highly linear signal separation. There has been little regard in the literature to the signal combiner implementation necessary to achieve the high power-added efficiency (PAE) of the LINC radio frequency (RF) power amplifier. Efficiency is not an intrinsic property of the combiner implementations, however, the combiner method is the single biggest contributor to efficient performance of a LINC RF power amplifier. This paper develops an analysis method that determines the efficiency of the LINC power amplifier as a function of the amplitude modulation statistics. This can be employed to design the RF communication system amplitude modulation characteristics and to tradeoff and optimize the RF transmitter PAE.

In this paper, an innovative approach to achieve broadband linear power amplifier (PA) with a continuous broadband is presented. The proposed method mainly depends on the theory of control of intermodulation products and harmonics. This method results in a continuous sweet spots over a wide bandwidth. Based on the continuous sweet spots, a suboptimal solution is derived for improving the efficiency and linearity of broadband PAs. To verify the effectiveness of this method, one broadband PA operating over 4.5–5.5[Formula: see text]GHz is developed and measured, it indicates that the peak output power of the PA is 35–57[Formula: see text]dBm for a small signal input with a gain of 12[Formula: see text]dB, and the peak drain efficiency (DE) of the PA is larger than 57% over the whole working band. However, when the PA is stimulated by a 5[Formula: see text]MHz two-tone signal input, we observe that the DE keeps above 38% under the condition of the measured third-order intermodulation distortion (IMD3) is not larger than [Formula: see text][Formula: see text]dBc.

In modern communication systems, envelope tracking (ET) is an important technology which can improve the efficiency of radio frequency (RF) linear power amplifier (LPA) significantly. A DC/DC converter is utilized in this technology to modulate the supply voltage of LPAs. It makes the supply voltage waveform track the envelope signal, thus the efficiency of the LPA can be largely improved. To track the high bandwidth envelope signal, the switching frequency of the DC/DC converter must be extremely high. GaN HEMT is a wide band gap device with excellent switching performance, therefore it is an ideal power semiconductor device for this application. In this paper, a 2-phase interleaved Buck converter based on GaN HEMT is introduced, which operates as envelope tracking power amplifier (ETPA). A detail analysis of modulation strategy used in multiphase interleaved Buck converter will be proposed and the optimal one will be selected. Moreover, an appropriate design of output filter is given to ensure the envelope tracking accuracy. Simulation results are provided to support the analysis and design. Finally, the proposed method is also verified by experimental results acquired from a prototype with peak power up to 125W and bandwidth up to 200kHz.

The efficiency of linear power amplifiers can be improved by modulating its supply voltage according to the peak value of the signal that is being amplified in a technique usually known as envelope tracking. High bandwidth dc/dc converters called envelope amplifiers (EAs) are used to carry out the supply modulation in an efficient manner. In the case of linear RF power amplifiers, the bandwidth requirements over the EA strongly depend on the signal being amplified: in modern telecommunication applications it can range from several hundred kilohhertzs to a few tens of megahertz. The path to achieve such bandwidths usually goes through increased switching frequencies and/or reduced ratio of switching frequency to converter bandwidth. However, these may lead to lower converter efficiency and increased distortion, making the design of EAs a challenging task. This paper addresses the analysis and design of the output filter for Buck converters operating as EA. The output filter must provide enough attenuation at the switching frequency and harmonics to guarantee a desired level of distortion while enabling tracking of wide-bandwidth envelope signals with high converter efficiency. This paper focuses on the use of high-order filters (up to sixth-order Bessel-Thomson, Butterworth, and Legendre-Papoulis filters) in a buck dc/dc converter working as an EA. The filters are analytically described and characterized, and a design procedure that takes into account the major design constraints is proposed, allowing the selection of the appropriate filter for a given application. The proposed analysis and design method are supported by simulation results, as well as by experiments obtained using a 1 MHz buck converter operating as an EA.

This paper presents the first linear bulk CMOS power amplifier (PA) targeting low-power fifth-generation (5G) mobile user equipment integrated phased array transceivers. The output stage of the PA is first optimized for power-added efficiency (PAE) at a desired error vector magnitude (EVM) and range given a challenging 5G uplink use case scenario. Then, inductive source degeneration in the optimized output stage is shown to enable its embedding into a two-stage transformer-coupled PA; by broadening interstage impedance matching bandwidth and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured $P_{\text {out}}$ /PAE at −25 dBc EVM for a 250 MHz-wide 64-quadrature amplitude modulation orthogonal frequency division multiplexing signal with 9.6 dB peak-to-average power ratio. The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6 dB back-off from saturation. To the best of the authors’ knowledge, these are the highest measured PAE values among published ${K}$ - and Ka -band CMOS PAs.

In this paper, a novel load-mismatch tracking digital predistortion (DPD) technique is proposed for linearizing mobile-terminal power amplifiers (PAs) under varying load-mismatch conditions. A time-domain poly-harmonic distortion (TD-PHD) model is discussed first for the behavioral modeling and linearization of PA under mismatch, followed by a practical model construction method. Then, the proposed DPD technique is derived based on the superposition principle, which enables automatic and fast adjustments of its coefficients to adapt to the PA's nonlinear characteristics under different load-mismatch conditions without re-identification of the DPD model. Experimental validations on a mobile-terminal PA module at 4.6 GHz with a 100 MHz 5G NR signal show that the proposed DPD technique realizes excellent linearization performance among a wide load-impedance varying range with low complexity.

OFDM has Major disadvantage is that it leads to high Peak to Average Power Ratio (PAPR) which is consider to be as the main implementation drawback. In this paper we are discussing about PAPR which affects the performance and efficiency of Power Amplifier (PA) and its influence by utilizing the Selective Mapping (SLM) technique in OFDM system for reduction of PAPR. the idea for improved SLM produces several independent signals based on converting the original data lock into many independent signal and then the signal has lowest PAPR that specific signal is transmitted. Also data rate trade-off exist at the receiver end when side information is detected for the recovery of data block. which leads to the reduction of data rate. Improved SLM techniques for reducing the PAPR is the most promising reduction technique in its non-uniform phase factor for PAPR reduction in multicarrier OFDM system. Furthermore the estimate expression by using Complementary Cumulative Distribution Function (CCDF) for PAPR has been discussed. Simulated results demonstrate that OFDMA signals using improved SLM technique carried significant effects in reduction of PAPR in OFDM system.

The blower with Active Magnetic Bearing (AMB) has the advantage of high speed, high reliability, small size, good adaptability. Power amplifier is an important part of the magnetic bearing system, directly determines the magnetic bearing system performance. The three-level PWM signal generation algorithm is analyses in this paper, and the IR2113 gate driven circuits with a negative bias is designed, and build a three-level magnetic bearing power amplifier. The gate driven signal of circuit is test, and entire power amplifier tracking step signal and sinusoidal signal also be test, the test results indicate that the three-level power amplifier meet the design requirements. At last, the power amplifier application on the blowers with AMB successful. Introduction Active Magnetic Bearings (AMB) using electromagnetic force to suspend rotor, with no friction loss, no lubrication, high-speed, non-polluting characteristics.The blower with AMB has the advantage of high speed, high reliability, small size, good adaptability Power amplifier is an important part of the overall magnetic bearing system, directly determines the magnetic bearing system performance . Depending on the realization of the principle, magnetic bearings power amplifier divided into linear power amplifier and switching power amplifier. With respect to the linear power amplifier, switching power amplifier has the advantage of low power consumption and high conversion efficiency; occupy a dominant position in large power amplifiers. Switching power amplifier can be divided into two-level amplifier switching amplifier and three-level switching amplifier depending on the switching signal. In two-level switching amplifier, the magnitude of current ripple is related to the DC voltage. Increases the DC voltage to improve the dynamic characteristics of the system, it will increase the electromagnetic coil current ripple at the same time. The current ripple of three-level switching power amplifier is not only smaller than the two-level power amplifier, but also nothing affected by the DC voltage , and therefore more suitable for high-power active magnetic bearings. In this paper, using FPGA chip to generate three-level switching signals, half-bridge circuit using IGBT modules and IGBT gate drive circuit is designed based on the drive requirements. The Three-level PWM Signal Generation Algorithm: D2 L Drive circuit FPGA Current sensor feedback AD circuit A D1 Vref S1 S2 I Reference signal Q1

Shortwave power amplifiers (PAs) are the most important nonlinear components in shortwave communication systems. It will generate significant intermodulation distortion (IMD) resulting in adjacent channel interference and higher bit-error rate when multiple nonconstant envelope modulation signals input into nonlinear PAs. Linearization techniques are necessary to compensate these undesired nonlinear effects. Among a variety of linearization techniques, digital predistortion technique has difficulties in modeling PAs and predistorter accurately and identifying systems. In this paper, we proposed a predistortion linearization method combined measured data with characteristics of shortwave PAs, which is suitable for “multi-objective” excitated memory shortwave PAs.