Load-Mismatch Tracking Digital Predistortion for Mobile-Terminal Power Amplifiers

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), [Formula: see text]) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR [Formula: see text]50[Formula: see text]dBc, at 10[Formula: see text]W LTE modulated PA output, antenna point and PA output power of 39.5[Formula: see text]dBm.

<span lang="EN-US">In this paper, a low-complexity model is proposed for linearizing power amplifiers with memory effects using the digital predistortion (DPD) technique. In the proposed model, the linear, low-order nonlinear and high-order nonlinear memory effects are computed separately to provide flexibility in controlling the model parameters so that both high performance and low model complexity can be achieved. The performance of the proposed model is assessed based on experimental measurements of a commercial class AB power amplifier by applying a single-carrier wideband code division multiple access (WCDMA) signal. The linearity performance and the model complexity of the proposed model are compared with the memory polynomial (MP) model and the DPD with single-feedback model. The experimental results show that the proposed model outperforms the latter model by 5 dB in terms of adjacent channel leakage power ratio (ACLR) with comparable complexity. Compared to MP model, the proposed model shows improved ACLR performance by 10.8 dB with a reduction in the complexity by 17% in terms of number of floating-point operations (FLOPs) and 18% in terms of number of model coefficients.</span>

This paper proposes a digital predistortion (DPD) technique to improve linearization performance when the power amplifier (PA) is driven near the saturation region. The PA is a non-linear device in general, and the nonlinear distortion becomes severer as the output power increases. However, the PA’s power efficiency increases as the PA output power increases. The nonlinearity results in spectral regrowth, which leads to adjacent channel interference, and degrades the transmit signal quality. According to our simulation, the linearization performance of DPD is degraded abruptly when the PA operates in its saturation region. To relieve this problem, we propose an improved DPD technique. The proposed technique performs on/off control of the adaptive algorithm based on the magnitude of the transmitted signal. Specifically, the adaptation normally works for small and medium signals while it stops for large signals. Therefore, harmful coefficient updates by saturated signals can be avoided. A computer simulation shows that the proposed method can improve the linearization performance compared with the conventional DPD method in highly driven PAs.

A digital predistortion (DPD) technique based on an iterative adaptation structure is proposed for linearizing power amplifiers (PAs). To obtain proper DPD parameters, a feedback path that converts the PA’s output to a baseband signal is required, and memory is also needed to store the baseband feedback signals. DPD parameters are usually found by an adaptive algorithm by using the transmitted signals and the corresponding feedback signals. However, for the adaptive algorithm to converge to a reliable solution, long feedback samples are required, which increases hardware complexity and cost. Considering that the convergence time of the adaptive algorithm highly depends on the initial condition, we propose a DPD technique that requires relatively shorter feedback samples. Specifically, the proposed DPD iteratively utilizes the short feedback samples in memory while keeping and using the DPD parameters found at the former iteration as the initial condition at the next iteration. Computer simulation shows that the proposed technique performs better than the conventional technique, as the former requires much shorter feedback memory than the latter.

In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2 and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.

The inherent nonlinear behavior exhibited by power amplifiers (PAs) in saturation mode is a major impediment in wireless systems to achieve higher power efficiency, and higher spectral efficiency. Although PA behavioral modeling and digital predistortion (DPD) techniques are widely utilized at transmitter to characterize and linearize such distorted nonlinear output of PAs, the nonlinear distortions with memory effects have become more severe due to simultaneous strong crosstalk between multiple PA branches in multiple-input multiple-output (MIMO) arrays. Furthermore, current multi-input behavioral models suffer from a sharp increase in number of coefficients as the number of transmitter path increases in MIMO. In overcoming these challenges, we propose a decomposed cross-correlation based single-input-single-output (CC-SISO) behavioral modeling architecture. The proposed solution utilizes a low-cost, novel cross-correlation based method to estimate and cancel the simultaneous nonlinear and reverse crosstalk from multiple PA branches. Once the crosstalk is mitigated, the MIMO DPD can be implemented with single-input DPD blocks which significantly reduces the complexity. Furthermore, CC-SISO DPD eliminates the requirement for signal feedback paths before and after the PA, and thus reduces overall hardware implementation complexity. Through simulations, we demonstrate that the proposed CC-SISO architecture can reduce the overall complexity of state-of-art multi-input DPD models for MIMO systems.

An adaptive digital predistortion (PD) technique is proposed for linearization of power amplifiers (PAs) in multiple-input multiple-output (MIMO) transmitters. Instead of constructing a separate feedback path at each PA, we propose a PD technique based on a combined feedback, which adds all the PAs' outputs to form a single feedback. We develop an algorithm for finding the multiple PA characteristics jointly from the combined feedback. The PD parameters are calculated from the identified PA characteristics. Although the proposed method requires more computations for PA identification than the conventional method, its hardware implementation is much simpler and can overcome the crosstalk problem of a radio frequency (RF) selector, which is necessary for multiple feedback selection. The simulation results show that, despite its simple structure, the linearization performance of the proposed method is almost the same as the separate multiple feedback method.

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

We consider digital predistortion (DPD) for linearizing power amplifiers (PAs) of hybrid MIMO systems with subarrays. Designing such a DPD scheme is difficult because one DPD should linearize all PAs of a subarray whose beamforming coefficients are time-varying. We develop an adaptive DPD technique for each subarray based on direct learning method minimizing the sum of squared errors between the input and output signals of PAs. Use of the least mean square (LMS) Newton algorithm is proposed to adaptively control the DPD parameters. It is shown that the proposed DPD can simultaneously linearize multiple PAs in a subarray irrespective of its beamforming coefficients. Computer simulation results demonstrate that the proposed scheme can perform better than an alternative scheme that designs the DPD based on one of the PA outputs and uses the resulting DPD for all PAs of the subarray.

The paper presents the results of laboratory studies on influence of DC transistor operating conditions both on power amplifier (PA) linearity and effectiveness of digital predistortion procedure. The impact of DC operating conditions of 10 W GaN HEMT power amplifier on nonlinearity factors without and with digital predistortion (DPD) were investigated. The obtained results show that there is an additional improvement in adjacent channel leakage ratio (ACLR) of the order of a few dB only by an increase in the quiescent drain current of PA transistor. However, some noticeable improvement of ACLR with significant increase in PA power added efficiency (PAE) is obtained for PA with digital predistortion.

Future generations of wireless communications are expected to place increasing burdens on the efficiency and linearity of power amplifiers, due to the use of more complex multi-carrier waveforms and OFDM. This has implications for the design of transmitters in portable/mobile devices as well as base stations and access points. This paper will summarize the digital predistortion techniques that can be employed to improve the performance of wireless power amplifiers.

Theoretically, memoryless nonlinear effect is the main concern for RF power amplifier (PA) modelling and analysis. However, the latest generation wireless communication systems, such as Wi-Fi, WiMAX and LTE, using wider bandwidth, add new problems for the analysis of RF PAs, which is the memory effect associated with the bandwidth. The memory effect causes additional distortion to the PA and affects the performance of digital predistortion (DPD) design. Previously, we predicted the memoryless spectrum regrowth of a PA related to its intercept points up to arbitrary high order for a few of wireless communication signals, such as TDMA, CMDA and OFDM. In this letter, we propose a simplified Hammerstein structure-based method to consider the memory effect as well in order to analyse the nonlinear characteristic of PAs more precisely and completely. The simplification greatly reduced the complexity of classic Hammerstein system identification for PAs. The result will be useful in the analysis of RF PAs with memory effect and the proposed PA model is intended to be used in predistorter design for modern wideband wireless communication systems.

The crosstalk and transceiver noise is an intrinsic part of the multiple-input and multiple-output (MIMO) System, becoming more prominent in low-cost systems. Moreover, the power amplifiers (PAs) cause nonlinearity, propagating to the complete chain. The conventional techniques do not provide the joint method for crosstalk, transceiver noise, and PA nonlinearity. This results in the performance limitation of the digital predistortion (DPD). Hence we propose a wavelet multiscale principal component analysis (PCA) based technique to deal with such problems (crosstalk, transceiver noise, and system nonlinearities). It is reported using measurement and simulation that numerical stability issue is no longer an issue when wavelet multiscale PCA-based DPD is applied. The effect of wavelet multiscale PCA on bit-resolution of DPD is shown to be better than established DPD Models. On a field-programmable gate array and direct conversion transceiver-based platform, the performance of the proposed model is analyzed using PA. Parameters like normalized mean square error have shown an improvement of around 23 dB and adjacent channel error power ratio has shown an improvement of around 22 dBc for a ZX60-V63+ power amplifier using LTE-OFDM signals.

This paper presents adaptive phase-only memory digital pre-distortion (DPD) and gain/phase/delay imbalance correction techniques for outphasing power amplifiers (PAs). Least squares adaptation is used for the phase-only DPD and imbalance correction techniques. The performance of these techniques is verified by co-simulations and measurements of an outphasing PA implemented with two identical class-F PAs and a Chireix combiner. The Chireix combiner with compensating stubs added to achieve high efficiency introduces nonlinearity. The proposed adaptive phase-only memory DPD corrects for the nonlinearity due to the Chireix combiner. The proposed gain/phase/delay imbalance correction technique achieves total lower/upper adjacent channel power ratio (ACPR) improvements of 43.8/37.6 dB for 5-MHz and 46.2/38.3 dB for 10-MHz long-term-evolution signals in measurements. The fractional-sample delay imbalance correction reduces distortion at low input amplitudes and demonstrates on the order of a 10-dB ACPR improvement compared to full-sample delay imbalance correction.

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