Distributed Digital Control of Modular-Based Solid-State Transformer Using DSP+FPGA

In this paper, we describe the multiple biometric recognition system based on 32 bit floating-point digital signal processor (DSP) and field programmable gates array (FPGA). In addition, it has the function of real-time display, which can help the users easily capture the perfect image that they need. Different from other platforms of using DSP and FPGA, we have two kinds of parallel bus interfaces between them, the EMIF and HPI interface. With the help of the Hardware Description Language (HDL) Verilog HDL, we make it true that the DPS and FPGA can co-process the matching algorithms. Comparing with the matching time that processes only by the DSP, the co-processing is more efficient than the processing only by one processor. Besides, we leave several parallel and series interfaces in our board for the future use. Therefore, our system can be applied to many different digital signal processing domains and provide them an excellent computing platform.

A Solid-State Transformer as Enabling Technology for Microgrids for Integration into the Power Distribution System: An Overview

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

The development of floating point digital signal processors (DSP) has led to a significant improvement in digital signal processing. This paper presents the application of a floating point DSP to the real time data processing and control of a dynamic robot measurement system, which is based on a single laser beam that is deflected over a mirror mounted to a beam steering mechanism. The specifications with regard to high accuracy of the measurement system and the cycle time for the numerous calculations that are performed to acquire the desired measurement data are reached with dedicated data acquisition modules that are connected via a 32 bits bus to a DSP. This configuration allows measurements with more than 10 kHz sampling rare and the execution of a sophisticated prediction control algorithm at the same rate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, a new motion control hardware architecture is proposed for improved motion performance of robotic manipulators during high speed motion. The main idea is to remove the servo control loop from the DSP (digital signal processor) to a FPGA (field programmable gate array), and utilize the high speed hardwired logic of the FPGA to enhance the computation capability and relieve the computing load on the DSP. The control algorithm is partitioned into a linear portion and a nonlinear portion. The linear portion with position/velocity feedback represents the major control loop and is implemented in the FPGA. The nonlinear portion acts as dynamic compensation to the linear portion to perform complex modeling related calculations, and is implemented in the DSP. A new FPGA-based motion control IC is designed to realize this new control hardware structure. Experiments were conducted on a Yamaha robot manipulator to compare new control architecture and the existing one, when the same control algorithm was used. Experimental results demonstrate that the proposed new control architecture exhibits much improved motion performance especially during high-speed motions

This paper proposes a development of Pulse-Width Modulation (PWM) switching signals based on Field Programmable Logic Array (FPGA) and Digital Signal Processor (DSP) to control multi-input interleaved DC/DC converter (MIC). The proposed PWM signals for the MIC do not only require a control of duty cycle, but also operation at different PWM frequency. In order to solve this problem, a simple programmable control scheme using a digital controller can be employed to facilitate the realization of PWM signals generation. The PWM signals are designed by using Altera Cyclone II FPGA board. The duty cycle employed to regulate output voltage is attained from the dSPACE DS1103 board using a Proportional-Integral (PI) controller. This paper also highlights design guidelines, simulation and experimental results. Experiment results show that the proposed DC converter can be driven by PWM signals, by integration of both controllers.

This article proposes a Distributed-control Architecture (D-CA) and an operation sequence with start-up strategies for a Digital Signal Processor (DSP)-based Solid-State Transformer (SST). Although various control techniques for SSTs have been reported in earlier studies, there is still a lack of research covering comprehensive content, including hierarchical control architectures and operation sequences with start-ups considering the implementation of DSPs. Therefore, this article addresses the following factors of SST. First, the D-CA is described for the design of the hierarchy between control boards. With the D-CA, because sub-boards are in charge of their corresponding DC-link voltage balancing control individually, the computational burden on the master board can be reduced. Second, the operation sequence of the SST system is explained based on the SST with D-CA. The step of DC-link voltage balance is considered throughout the entire operation sequence for safe driving. Furthermore, the PWM start-up strategies for a Cascade H-bridge Multilevel (CHM) converter and Dual Active Bridge (DAB) converter are proposed to prevent switching pulse errors caused by DSP operating characteristics. These start-up strategies reduce the current surges. The validity of the proposed D-CA and operation sequence with start-up strategies are verified by experimental results.

In this paper, we describe the Iris recognition system based on 32-bit floating point digital signal processor (DSP) and 32-bit advanced RISC machines(ARM). Iris recognition is more accurate and stability compare to other biometric recognition techniques and it is also a remote recognition using machine vision, meanwhile it is a biometric recognition technique without invasion.This paper design an embedded iris recognition system base on ARM and DSP. The system has integrated with image acquisition, image process, image recognition and has advantages of high speed, small size, low power requirement and etc.

The requirement for efficient digital signal processing (DSP) systems and its solutions increases highly over the last few years. DSP techniques as well as its algorithms are necessary for day to day life tool namely smartphone, set-top unit (STU), video and acoustic players, digital cameras, digital television, etc. This paper describes a comparative study on knowledge-based digital filter structure namely transposed form, direct form, and systolic array. To implement the parallel processing the systolic array structure is often used. A Goertzel algorithm is implemented in the field-programmable gate array (FPGA) Altera EP4CE115F29C7 device which is used to determine the discrete Fourier transform (DFT). Finally, filtering technique is implemented efficiently by dividing filter coefficients and data into odd and even which increases the computational speed. The computational speed and functional verification results are achieved by using MATLAB. The Altera DSP builder and Simulink are used for the implementation of Goertzel algorithm. The 64-tap systolic low-pass filter structures offer 213.97-μs-less delay than the transposed form, 1700 μs, and direct form, 3900 μs, structures. Similarly for 2048-tap low-pass filter using sub-filter offers 49.397-ms computational speed and direct filtering offers 53.257 ms.

This paper demonstrates that oversampling improves the performance of digitally implemented space vector modulation. Using a field programmable gate array (FPGA) instead of a digital signal processor (DSP) or microcontroller allows the discrete algorithm to be executed in parallel instead of in series, increasing the algorithm speed considerably. As a result the reference signal can be sampled many times during any single switching period, converging on the performance of naturally sampled continuous signals. This paper shows experimental evidence that the phase delay of the output signal compared to the reference signal is significantly reduced by oversampling the reference signal. Additionally its gain with respect to the reference signal and its spectrum at low frequency are improved.

Current legislation in European countries, as well as in other parts of the world, is putting stricter limits on pollutant emissions from road vehicles. This issue, in conjunction with the increase awareness of consumer for the environmental problems, will require the development of new clean propulsion systems in disruption with the current mobility solutions based on internal combustion engine. Electric, hybrid and fuel-cells vehicles (Chan, 2007) are now recognized as an indispensable mean to meet the challenges associated with sustainable mobility of people and goods. In this paradigm shift, the electric motor (EM) will assume a key role in the propulsion of future vehicles and, unlike vehicles based on internal combustion engines, the high energy and power densities will facilitate the development of new powertrains configurations. In particular, multi-motor configurations, where several EMs are allocated to each driven wheel of the vehicle, represent an attractive configuration for electric vehicles (EVs), due to the independent wheel torque control and the elimination of somemechanical systems, like the differential. These features, allied with the fast dynamics of EMs, are being explored to increase the vehicle maneuverability and safety (Geng et al., 2009) and improve the performance of the EV traction system (Hori, 2004). To cope with this rise in functional and computational complexity that current (and future) EVs require, in this work we explore the new Field-programmable Gate Array (FPGA) platform to address the powertrain control, i.e. involving the electric motor and the power converters control, of multi-motor EVs. In the past two decades, motor control applications have been dominated by software based solutions implemented in DSPs (Digital Signal Processors), due to the low cost and ease of programming (Cecati, 1999). However, these DSP solutions are facing increasing difficulties to respond to the ever-increasing computational, functional and timing specifications that modern industrial and vehicular applications require (Monmasson & Cirstea, 2007). For instance, when single-coreDSP based solutions needs to incorporate complex and time-critical functions, e.g. multi-motor control, the sequential processing of this approach decrease the controller bandwidth (see Fig. 1), which may compromise the application timing specification. Multi-core DSPs are a possible alternative to address this concern, but they also add costs and interconnection complexity. Consequently, in the last years, FPGAs received an increased interest by the academy and industry as an option to offload time-critical tasks from the DSPs (Lopez et al., 2008; Rahul et al., 2007; Ying-Yu & Hau-Jean, 1997), or even replace the DSPs control platform by a System on Chip (SOC) based on FPGAs (Idkhajine et al., 2009). 7

Innovation Partners proposed and successfully demonstrated in this SBIR Phase I grant a software/hardware co-design approach to reduce both the difficulty and time to implement Field Programmable Gate Array (FPGA) solutions to data acquisition and specialized computational applications. FPGAs can require excessive time for programming and require specialized knowledge that will be greatly reduced by the company's solution. Not only are FPGAs ideal for DAQ and embedded solutions, they can also be the best solution to specialized signal processing to replace Digital Signal Processors (DSPs). By allowing FPGA programming to be done in C with the equivalent of a simple compilation, algorithm changes and improvements can be implemented decreasing the life-cycle costs and allow subsitution of new FPGA designs staying above the technological details.

Field Programmable Gate Arrays (FPGAs) have gained popularity because their reconfigurability can speed up development and verification with relatively low cost. However the deep level of understanding required on hardware logic programming has discouraged many software engineers. An interface between host devices and FPGAs to enable designing and programming FPGAs using a software programming standard and encapsulating hardware details is much desired. In this paper we evaluate leveraging Open Computing Language (OpenCL) to rapidly design FPGAs, considering both hardware logic utilization efficiency and computing performance. On a heterogeneous computer system consisting of ARM processors and Altera FPGA, we execute an OpenCL host program on the ARM processors and an OpenCL kernel on the FPGA, to compute a parametrizable two-dimensional Mandelbrot fractal. We explore three design aspects of adjusting OpenCL work-group size, coalescing memory access, and replicating compute units to improve the FPGA computation performance. After optimizing the core algorithm, we efficiently reduced the logic utilization and Digital Signal Processing (DSP) blocks required for a single compute unit, and successfully increased the number of replicated compute units from four to six, thus delivering a 1.5X increase of parallel computation capacity of the FPGA, and improving the computing speed by 1.5X and memory bandwidth by 1.7X.

This paper presents the implementation and experimental details of a real-time digital simulator designed for representing a Distribution Static Compensator (D-STATCOM) interfaced with a digital controller. Real-time simulation using conventional fixed time-step integration algorithms can lead to erroneous results due to the lack of synchronism between the simulator time-step and the discrete switching signals coming from the digital controller. The real-time simulation algorithm implemented in this paper overcomes the drawbacks of a fixed time-step algorithm. The real-time algorithm relies on precise registration of timing of the incoming discrete firing pulses and a subsequent correction procedure to calculate the system state. This approach has been implemented on a hybrid digital processing platform comprising of a Digital Signal Processor (DSP) and a Field Programmable Gate Array (FPGA). The platform represents both the power electronic system and the digital control system. Experimental results, for a 5 kV A D-STATCOM system, in verification of the real-time simulator results are also provided.

Programmable logic offers an alternative solution for the computationally-intensive functions found in digital signal processing (DSP). Programmable logic can provide increased DSP system performance at reduced system cost. Programmable logic combines the flexibility of a general purpose DSP plus the speed, density, and low cost of an ASIC implementation. In some applications, programmable logic replaces the DSP processor entirely. In others, programmable logic works in conjunction with the DSP processor, offloading the computationally-intensive function and freeing the processor for other functions. This paper describes an alternative to traditional, general-purpose DSP processors. Programmable logic can implement functions beyond the capabilities of today's DSP processors. Field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs) potentially provide performance increases of an order of magnitude over traditional DSPs with the same flexibility.