FPGA based digital implementation of naturally sampled space vector modulation

The pulse width modulation (PWM) is an important segment in power electronic inverters and multilevel inverters (MLIs) design. The space vector modulation (SVM) methods own distinct advantages over other PWM methods. However, MLI SVM has involved more mathematics in their executions. Hence, the digital signal processors (DSPs) or field programmable gate arrays (FPGAs) based digital implementations are highly preferred for MLI SVM realizations, which require exceptional properties. The conventional MLI SVMs use complex mathematical functions to solve their internal functions to identify the space vector diagram (SVD) sub-triangle and over modulation boundary switching on-times. Particularly these are the changes in the position of reference vector with respect to their sub-triangle positions involving higher mathematical functions. This paper proposes a simplified three-level MLI SVM that reduces the sub-triangle and over modulation switching on-time calculations with reduced mathematical functions. The proposed MLI SVM is derived based on two-level SVM without changing the reference vector position, unlike the traditional approaches. This helps in extending the SVM for any n-level inverter with additional LUTs. The detailed theoretical study, MATLAB-Simulink system generator simulations and Xilinx FPGA family SPARTAN-III-3A based experimental implementations are done with three-level neutral point MLI fed induction motor drive. The theoretical design, analysis, and experimentation results validate the advantages of the proposed PWM design and its implementation. In addition, the proposed implementation is executed from the MATLAB Xilinx system generator directly into target FPGA, which makes it faithful, efficient and minimizes the time spent.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

In this paper, a new design method of Direct Torque Control using Space Vector Modulation (DTC-SVM) of an Induction Machine (IM), which is based on Fault Tolerant Control (FTC) is proposed. Due to its complexity, the FTC implemented on a microcontroller and a Digital Signal Processor (DSP) is characterized by a calculating delay. To solve this problem, an alternative digital solution is used, based on the Field Programmable Gate Array (FPGA), which is characterized by a fast processing speed. However, as an FPGAs increase in size, there is a need for improved productivity, and this includes new design flows and tools. Xilinx System Generator (XSG) is a high-level block-based design tool that offers bit and cycle accurate simulation. This tool can automatically generate the Very High-Density Logic (VHDL) code without resorting to a tough programming, without being obliged to do approximations and more we can visualize the behavior of the machine before implementation which is very important for not damage our machine. Simulation and experimental results using Hardware In the Loop (HIL) of the FTC based DTC-SVM is compared with those of the conventional DTC. The comparison results illustrate the reduction in the torque and stator flux ripples. Our purpose is to reveal our algorithm efficiency and to show the Xilinx Virtex V FPGA performances in terms of execution time.

This paper proposes a distributed digital control architecture of a modular-based solid-state transformer (SST) using a digital signal processor (DSP) and a field-programmable gate array (FPGA). In particular, the three-stage SST based on a modular structure is the topology of most interest because of its superior controllability. In order to make the modular-based SST, the digital implementation is inevitable to achieve higher performances, improved reliability, and an easy development. In addition, the modular-based SST requires enough capacity for implementing complex control algorithms, multiple interfaces, and a large number of internal variables. In this paper, a digital control platform for the modular-based SST is built using a floating-point DSP and an FPGA that operate cooperatively. As a result, the main control algorithms are performed by the DSP, and the simple logical processes are implemented in the FPGA to synthesize the suitable gating signals and control external devices, respectively. The proposed implementation method enables high-switching-frequency operation, multitasking, and flexible design for the modular-based SST. Experimental results are presented to verify the practical feasibility of the proposed technique for the modular-based SST.

Field Programmable Gate Arrays (FPGAs) have gained popularity because their reconfigurability can speed up development and verification with relatively low cost. However the deep level of understanding required on hardware logic programming has discouraged many software engineers. An interface between host devices and FPGAs to enable designing and programming FPGAs using a software programming standard and encapsulating hardware details is much desired. In this paper we evaluate leveraging Open Computing Language (OpenCL) to rapidly design FPGAs, considering both hardware logic utilization efficiency and computing performance. On a heterogeneous computer system consisting of ARM processors and Altera FPGA, we execute an OpenCL host program on the ARM processors and an OpenCL kernel on the FPGA, to compute a parametrizable two-dimensional Mandelbrot fractal. We explore three design aspects of adjusting OpenCL work-group size, coalescing memory access, and replicating compute units to improve the FPGA computation performance. After optimizing the core algorithm, we efficiently reduced the logic utilization and Digital Signal Processing (DSP) blocks required for a single compute unit, and successfully increased the number of replicated compute units from four to six, thus delivering a 1.5X increase of parallel computation capacity of the FPGA, and improving the computing speed by 1.5X and memory bandwidth by 1.7X.

Low switching frequency is always used in an electric rail traction induction motor control system, in order to reduce switching losses and increase system reliability. But under low switching frequency, the conventional single pulse width modulation (PWM) technique for the whole speed region will produce a large number of harmonic components, which in turn cause motor heating, torque ripple, and other adverse effects. In this paper, a hybrid PWM technique formed by merging carrier-based asynchronous and synchronous modulation and optimal synchronous modulation is proposed to achieve low losses and total harmonics based on very low switching frequency. A simple low-cost and low-power digital signal processor (DSP) and field programmable gate array (FPGA) hybrid hardware structure is then adopted for implementing the technique, which fully utilizes advantages and resources of each processor. Total harmonic distortion of the system can hence be reduced by operating with the high-precision hybrid PWM, while not compromising the multirate and multitask processing requirements of traction control. Detailed implementations in both DSP and FPGA with high accuracy, low usage of resources, and computational burden are then described, focusing particularly at the smooth transitions among different PWM schemes. Simulations and experiments are eventually performed with results captured for validating the presented hybrid PWM technique.

Innovation Partners proposed and successfully demonstrated in this SBIR Phase I grant a software/hardware co-design approach to reduce both the difficulty and time to implement Field Programmable Gate Array (FPGA) solutions to data acquisition and specialized computational applications. FPGAs can require excessive time for programming and require specialized knowledge that will be greatly reduced by the company's solution. Not only are FPGAs ideal for DAQ and embedded solutions, they can also be the best solution to specialized signal processing to replace Digital Signal Processors (DSPs). By allowing FPGA programming to be done in C with the equivalent of a simple compilation, algorithm changes and improvements can be implemented decreasing the life-cycle costs and allow subsitution of new FPGA designs staying above the technological details.

Current legislation in European countries, as well as in other parts of the world, is putting stricter limits on pollutant emissions from road vehicles. This issue, in conjunction with the increase awareness of consumer for the environmental problems, will require the development of new clean propulsion systems in disruption with the current mobility solutions based on internal combustion engine. Electric, hybrid and fuel-cells vehicles (Chan, 2007) are now recognized as an indispensable mean to meet the challenges associated with sustainable mobility of people and goods. In this paradigm shift, the electric motor (EM) will assume a key role in the propulsion of future vehicles and, unlike vehicles based on internal combustion engines, the high energy and power densities will facilitate the development of new powertrains configurations. In particular, multi-motor configurations, where several EMs are allocated to each driven wheel of the vehicle, represent an attractive configuration for electric vehicles (EVs), due to the independent wheel torque control and the elimination of somemechanical systems, like the differential. These features, allied with the fast dynamics of EMs, are being explored to increase the vehicle maneuverability and safety (Geng et al., 2009) and improve the performance of the EV traction system (Hori, 2004). To cope with this rise in functional and computational complexity that current (and future) EVs require, in this work we explore the new Field-programmable Gate Array (FPGA) platform to address the powertrain control, i.e. involving the electric motor and the power converters control, of multi-motor EVs. In the past two decades, motor control applications have been dominated by software based solutions implemented in DSPs (Digital Signal Processors), due to the low cost and ease of programming (Cecati, 1999). However, these DSP solutions are facing increasing difficulties to respond to the ever-increasing computational, functional and timing specifications that modern industrial and vehicular applications require (Monmasson & Cirstea, 2007). For instance, when single-coreDSP based solutions needs to incorporate complex and time-critical functions, e.g. multi-motor control, the sequential processing of this approach decrease the controller bandwidth (see Fig. 1), which may compromise the application timing specification. Multi-core DSPs are a possible alternative to address this concern, but they also add costs and interconnection complexity. Consequently, in the last years, FPGAs received an increased interest by the academy and industry as an option to offload time-critical tasks from the DSPs (Lopez et al., 2008; Rahul et al., 2007; Ying-Yu & Hau-Jean, 1997), or even replace the DSPs control platform by a System on Chip (SOC) based on FPGAs (Idkhajine et al., 2009). 7

The requirement for efficient digital signal processing (DSP) systems and its solutions increases highly over the last few years. DSP techniques as well as its algorithms are necessary for day to day life tool namely smartphone, set-top unit (STU), video and acoustic players, digital cameras, digital television, etc. This paper describes a comparative study on knowledge-based digital filter structure namely transposed form, direct form, and systolic array. To implement the parallel processing the systolic array structure is often used. A Goertzel algorithm is implemented in the field-programmable gate array (FPGA) Altera EP4CE115F29C7 device which is used to determine the discrete Fourier transform (DFT). Finally, filtering technique is implemented efficiently by dividing filter coefficients and data into odd and even which increases the computational speed. The computational speed and functional verification results are achieved by using MATLAB. The Altera DSP builder and Simulink are used for the implementation of Goertzel algorithm. The 64-tap systolic low-pass filter structures offer 213.97-μs-less delay than the transposed form, 1700 μs, and direct form, 3900 μs, structures. Similarly for 2048-tap low-pass filter using sub-filter offers 49.397-ms computational speed and direct filtering offers 53.257 ms.

This work presents the hardware and software architecture for the detection of fractures and edges in materials. While the detection method is based on the novel concept of Low Transient Pulse (LTP), the overall system implementation utilizes two microelectronics technologies: Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The DSP carries out the analysis of the received signal at a much lower rate hence can accommodate a large number of signal channels. The FPGA runs at a higher frequency (62.5MHz) to generate the LTP signal and to calculate the envelope of the received signal (sampled at 1MHz). This research elaborates on designing a Quadrature AM (QAM) demodulator on the FPGA for the received signal from the ultrasound and for the detection of the presence of edges/fracture on the test materials. The complete system is designed and optimized in a high level Matlab\Simulink fixed point simulation. Different sub-blocks are then implemented and optimized on the FPGA where efforts are taken to maintain its accuracy with the simulated model. In this work, the technology is applied to determine the location of the Sawbone plate edges based on the received signals which are then passed through a QAM demodulator in the FPGA and a peak detector in the DSP to calculate the echo peak times.

The drives of power amplifiers of magnetic levitation servo spindle applied to micro EDM (Electron discharge machining) based on FPGA (Field programmable gate array) are developed. The drive module that produces the PWM (Pulse width modulation) waves that conform to the requirements of spindle power amplifiers involving three-level half bridge switch power amplifier, three-level full bridge switch power amplifier and motor power amplifier, according to input of action values from magnetic levitation servo spindle controller DSP (Digital signal processor) is designed. Multi-PWM producing algorithm by single timer with multi comparing nodes is proposed. After being applied to control system of magnetic levitation servo spindle, the drives accomplish conversion from DSP action values to PWM waves. The PWMs that drive radial coil current power amplifier have phase difference of 180°. The PWMs that drive axial coil current power amplifier have dead zone time and their wave shapes are complementary. The PWMs that drive the motor power amplifier conform to requirements of power amplifier chip LMD18200. Using FPGA to realize the drive function of spindle power amplifier makes the drive design more flexible, resource distribution of DSP more optimized, the task of algorithms running more centralized, and the drives module gets simpler and more reliable because the phase shift circuit and dead zone circuit are cancelled but the function of phase shift and dead zone is reserved.

In this paper, a new motion control hardware architecture is proposed for improved motion performance of robotic manipulators during high speed motion. The main idea is to remove the servo control loop from the DSP (digital signal processor) to a FPGA (field programmable gate array), and utilize the high speed hardwired logic of the FPGA to enhance the computation capability and relieve the computing load on the DSP. The control algorithm is partitioned into a linear portion and a nonlinear portion. The linear portion with position/velocity feedback represents the major control loop and is implemented in the FPGA. The nonlinear portion acts as dynamic compensation to the linear portion to perform complex modeling related calculations, and is implemented in the DSP. A new FPGA-based motion control IC is designed to realize this new control hardware structure. Experiments were conducted on a Yamaha robot manipulator to compare new control architecture and the existing one, when the same control algorithm was used. Experimental results demonstrate that the proposed new control architecture exhibits much improved motion performance especially during high-speed motions

This thesis aims to develop an embedded image processing board, which can be used to realize various image feature extraction and processing algorithms for robotic applications. The circuitry of this image board can be divided into two parts, one is for a digital signal processor (DSP) and the other for a field programmable gate array (FPGA). A low power, small size CMOS image sensor with YUV4:2:2 image format and 512x480 pixel size is adopted for image acquisition. The DSP module is mainly used for implementing image processing algorithms, while the FPGA module for lower level image processing and sensor control functions. In this work, the TMS320C6414TGLZ7 DSP from Texas Instruments Corporation and the EP2C35F672C6 FPGA from Altera Corporation were selected for the image board. In this work, speeded-up robust features (SURF) algorithm has been successfully realized on the developed image board. An USB interface with average throughput of 22MB/sec works to transfer acquired image frames and extracted SURF descriptors to a personal computer, where feature matching is executed. Experimental results show that the refresh period of frame grabbing is about 33.5ms. When the number of SURF descriptor is equal to 64, the computing time is about 417.5ms; when the number of SURF descriptor is equal to 199, the computing time is about 985ms. The typical matching rate varies from 70.2% to 20%, depending on the threshold of the patterns used in feature extraction.

In this paper, we describe the multiple biometric recognition system based on 32 bit floating-point digital signal processor (DSP) and field programmable gates array (FPGA). In addition, it has the function of real-time display, which can help the users easily capture the perfect image that they need. Different from other platforms of using DSP and FPGA, we have two kinds of parallel bus interfaces between them, the EMIF and HPI interface. With the help of the Hardware Description Language (HDL) Verilog HDL, we make it true that the DPS and FPGA can co-process the matching algorithms. Comparing with the matching time that processes only by the DSP, the co-processing is more efficient than the processing only by one processor. Besides, we leave several parallel and series interfaces in our board for the future use. Therefore, our system can be applied to many different digital signal processing domains and provide them an excellent computing platform.

In this paper, we propose a self referencing scheme for the reduced complexity parallel least mean square (RC-pLMS) adaptive beamforming algorithm as means of robustness against possible interruptions in the reference signal and its hardware implementation. The RC-pLMS is a single stage, non-blind, least mean square (LMS) algorithm with modified input vectors formed as a linear combination of the current and the previous input sample. In this context, its convergence and its stability are critically dependent on the availability of its reference signal and are known to severally degrade when discontinued. Thus, for robustness against the pre-mentioned and with respect to the RC-pLMS accelerated convergence and low residual error profile, we propose the use of it’s filtered output, as an alternative learning sequence, whenever the original reference signal is discontinued, i.e. self-referencing. The proposed self referencing approach is evaluated in infinite and finite precision modes on software and on hardware, i.e. Field Programmable Gate Array (FPGA), respectively. Hardware and software simulation validates the RC-pLMS robustness against different reference signal obstruction scenarios, through the use of the proposed self-referencing approach, while maintaining an accelerated convergence behavior, a low complexity architecture and a high precision beam pointing accuracy.KeywordsLMSParallel LMSRobust adaptive beamformingSelf referencingRC-pLMSDigital communicationFPGA