Hardware Implementation of FTC of Induction Machine on FPGA

This paper aims to propose and develop a research platform which can be utilized for rapid prototyping of control algorithms of power converters used in the field of renewable energy, such as the photovoltaic systems. This study investigates the use of the Field-Programmable Gate Array (FPGA) to control the DC/DC power converter and the voltage inverters used in solar photovoltaic pumping systems. The power circuit of the pumping system consists of a PV system, a DC/DC converter, a two-level voltage inverter and an induction motor. The control system is based on an MPPT control algorithm and a Direct Torque Control with a Space Vector Modulation (DTC-SVM) based on proportional-integral controllers. In order to perform the hardware in the loop, the power circuit is realized using the Simulink blocks and the control system is designed using the Xilinx System Generator (XSG) tool. The VHDL code and the bit stream file of the suggested control algorithms have been automatically generated using the XSG tool. The hardware co-simulation step is carried out in the laboratory utilizing an FPGA Virtex 5 ML 507 and the Matlab/Simulink environment. A comparative study between the classical DTC and the DTC-SVM is presented. The FPGA-performance in terms of computation power is demonstrated.

In this paper, a design method of direct torque control (DTC) of an induction machine, which is based on fuzzy logic control (FLC), is proposed. The FLC which is introduced to improve the DTC uses a reduced number of fuzzy inference rules that facilitates the reduction of the FLC computation time. The improvement is performed by reducing the torque and stator flux ripples in the induction machine drive. Then, a hardware description that is based on the VHDL hardware description language of the proposed design is presented and discussed. The techniques of the parallel architecture, direct computation, and modular architecture are adopted for the design of the controller. Simulation and experimental results of the DTFC are compared with those of the conventional DTC. The comparison results illustrate the reduction in the torque and stator flux ripples of the DTFC. The validity of the proposed method is confirmed by the simulation and experimental results.

The pulse width modulation (PWM) is an important segment in power electronic inverters and multilevel inverters (MLIs) design. The space vector modulation (SVM) methods own distinct advantages over other PWM methods. However, MLI SVM has involved more mathematics in their executions. Hence, the digital signal processors (DSPs) or field programmable gate arrays (FPGAs) based digital implementations are highly preferred for MLI SVM realizations, which require exceptional properties. The conventional MLI SVMs use complex mathematical functions to solve their internal functions to identify the space vector diagram (SVD) sub-triangle and over modulation boundary switching on-times. Particularly these are the changes in the position of reference vector with respect to their sub-triangle positions involving higher mathematical functions. This paper proposes a simplified three-level MLI SVM that reduces the sub-triangle and over modulation switching on-time calculations with reduced mathematical functions. The proposed MLI SVM is derived based on two-level SVM without changing the reference vector position, unlike the traditional approaches. This helps in extending the SVM for any n-level inverter with additional LUTs. The detailed theoretical study, MATLAB-Simulink system generator simulations and Xilinx FPGA family SPARTAN-III-3A based experimental implementations are done with three-level neutral point MLI fed induction motor drive. The theoretical design, analysis, and experimentation results validate the advantages of the proposed PWM design and its implementation. In addition, the proposed implementation is executed from the MATLAB Xilinx system generator directly into target FPGA, which makes it faithful, efficient and minimizes the time spent.

In this paper a study is presented about the reduction of electromagnetic interference (EMI) in Direct Torque Control (DTC) method by the means of chaotic space vector modulation. Space Vector Modulated Direct Torque Control (SV-DTC) is a method developed to reduce current and moment fluctuations which stem from the hysteresis controllers used in classical DTC method. The switching frequency amplitude was changed chaotically in a Space Vector Modulated Direct Torque Control (FFSV-DTC) having a Fixed switching frequency, and Chaotic Space Vector Modulated Direct Torque Control (CAFSV-DTC) method having chaotic amplitude modulated switching frequency was obtained. CAFSV-DTC method was suggested to reduce EMI, acoustic noise and current harmonics which occur in FFSV-DTC method. For this purpose, the proposed CAFSV-DTC method, using a Permanent Magnet Synchronous Motor (PMSM) drive, is compared to Random Amplitude Frequency method (RSV-DTC) and FFSV-DTC. Simulation results indicate that the proposed method yields better results. DOI: http://dx.doi.org/10.5755/j01.eee.22.1.14097

Field Programmable Gate Arrays (FPGAs) have become a popular medium for the implementation of many digital circuits. Mapping applications into FPGAs requires a set of efficient Computer-Aided Design (CAD) tools to obtain high-quality Integrated Circuits (ICs). One critical issue of FPGA implementation is the quality and efficiency of associated CAD algorithms. In this paper, we are interested in investigating clustering algorithms aspect to optimize Mesh of Clusters (MoCs) FPGA performance. In fact, the way we distribute Logic Blocks (LBs) between FPGA clusters has an important impact on performance. In this paper, we explore the effects of two clustering algorithms (First Choice (FC) and T-VPack) on MoCs FPGA architecture based only on short routing wires. This paper highlights and experimentally demonstrates that FC clustering algorithm ameliorates power consumption, area, critical path delay and energy by an average of 17%, 11%, 13% and 24% respectively compared to T-VPack for MoCs FPGA.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

Hardware-in-the-Loop (HWIL) simulation is becoming increasingly important for cost-effective testing of imaging infrared systems. DSTO is developing real-time scene generation and image processing capabilities within its HWIL simulation programs, based on the application of COTS desktop PCs equipped with Graphics Processing Unit (GPU) cards, and including limited use of Field Programmable Gate Arrays (FPGAs). GPUs and FPGAs are high-performance parallel computing machines but are fundamentally different types of hardware. To determine which hardware type should be used to implement a real-time solution of a given application, a methodology is required to expose the concurrency within the problem and to structure the problem in a way that can be mapped to the hardware types. In this paper we use parallel programming patterns to compare the architectures of recent generation GPUs and FPGAs. We demonstrate the decomposition of a parallel application and its implementation on GPU and FPGA hardware and present preliminary results.

Although software implementations of different image processing techniques are suitable for general-purpose use, in order to meet the real time requirements, an image processing technique needs to be realized in hardware. Field Programmable Gate Arrays (FPGAs) have many benefits in applications that include digital signal acquisition, but also processing of large data, especially in real time. Mainly due to the ever-decreasing cost and re-configurability, FPGAs have also found its place in digital signal processing (DSP). Xilinx System Generator is a tool from Xilinx that enables the Mathworks Simulink models to be adapted for FPGA design. For comparative study on several levels in edge detection, CT image of a brain with a tumor is used. Performances of gradient based edge detectors - Robert, Prewitt and Sobel were compared. Even from just visual analysis of results, it can be seen that Prewitt and Sobel methods give better results than Robert method. In contrast, the calculation of Robert operator is simpler in comparison to the other operators and occupies less resources, since only adder-subtractor logic is sufficient to detect the edges. As the implemented algorithms could be part of more complex systems for tumor detection, the design architecture used in this paper can be extended to be used in very complex real time image processing techniques.

The Space Vector Pulse Width Modulation (SVPWM) is possibly the best among all the PWM techniques for variable frequency drive applications. Unfortunately, the modulation algorithm is mainly implemented with software based on microcontroller or digital signal processors (DSP). These are software-based technique purely and obviously not an ideal solution. Employing Field Programmable Gate Array (FPGA) to realize SVPWM strategies provides advantages that it is considered as an appropriate solution to boost system performance of an SVPWM algorithm. Moreover, although in the literatures the implementation for three-phase SVPWM based on FPGA is not lacking, however all these designs are based on the conventional SVPWM without considering hardware-resource saving and not simple. This paper present a simple realization of 5-segment discontinuous SVPWM with a difference approach based on FPGA, in which the judging of sectors and the calculation of the firing time to generate the SVPWM waveform is simple, and also the switching losses is low. The proposed discontinuous SVPWM has been designed and successfully implemented by using APEX20KE Altera FPGA considering hardware-resource saving and has successfully driven a three phase inverter system with induction machine 1.5 kW as load.

This paper present the Field Programmable Gate Array (FPGA) realization of speed-sensorless Direct Vector Control (DVC) utilizing Extended Kalman Filter (EKF) with stator resistance estimation for Induction Motors (IMs). The EKF simultaneously estimates stator stationary axis components of stator currents and rotor fluxes, rotor angular velocity, load torque and stator resistance. The implemented speed-sensorless control system on FPGA also includes the model of IM to be controlled, so it is considered as a Hardware In the Loop (HIL) system. The FPGA is programmed via Very High Speed Integrated Circuit Hardware Description Language (VHDL). Comparison of the estimated states/parameters obtained from the EKF with the ones of the IM show the effectiveness of the FPGA implementation of the speed-sensorless DVC of IM in this study.

This paper demonstrates that oversampling improves the performance of digitally implemented space vector modulation. Using a field programmable gate array (FPGA) instead of a digital signal processor (DSP) or microcontroller allows the discrete algorithm to be executed in parallel instead of in series, increasing the algorithm speed considerably. As a result the reference signal can be sampled many times during any single switching period, converging on the performance of naturally sampled continuous signals. This paper shows experimental evidence that the phase delay of the output signal compared to the reference signal is significantly reduced by oversampling the reference signal. Additionally its gain with respect to the reference signal and its spectrum at low frequency are improved.

Field-Programmable Gate Arrays (FPGAs) are becoming an interesting component for heterogeneous computing systems in the post-Moore era thanks to their reconfigurable nature. The current generation of FPGAs includes specialized hard blocks for floating point operations, making them attractive for scientific computing. FPGA programming has historically been done in hardware description languages, which required a deep understanding of hardware design. Emerging high-level synthesis tools, such as Intel oneAPI and AMD Vitis™, provide a more common programming environment for FPGAs. In this paper, we explore the capabilities of FPGAs for acceleration in the context of nuclear particle transport simulators. As a case study, we implement XS-Bench in Intel oneAPI targeting FPGAs, including basic optimizations. We then compare the performance of Intel Stratix10 FPGA and Intel Xeon CPU-based systems and evaluate the viability of FPGA use in heterogeneous systems.

This paper explores the use of the Xilinx's system generator development tool for the implementation of control algorithms on Xilinx field programmable gate arrays (FPGA). The Simulink plug in complements traditional hardware description language (HDL) by providing a graphical language with a higher level of abstraction for the development of FPGA designs. After taking into consideration the challenges of converting control designs that have been implemented and verified within the Simulink environment to FPGA hardware implementation, a systematic approach is presented. As a case study, a FPGA implementation of a control system was derived and verified for a simulated unmanned ground vehicle (UGV). The design example demonstrates the validity of the presented method as an efficient and reliable method for rapid system prototyping for designs developed using the Simulink environment.

The designers of field programmable gate array (FPGAs) always devote to optimize the chip performance. The fabrication cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate ways of reducing FPGA power consumption so that they can also deploy in place of ASICs in portable energy constrained applications. Minimum energy delay point occurs in subthreshold region and subthreshold operation of circuits shows order of power saving over superthreshold circuits. Therefore, it is also important to investigate the possibility of extending the use of FPGA even in subthreshold region for ultra low power applications. This paper investigates the subthreshold performance of a basic FPGA building block-a Look up Table (LUT). It presents the performance optimization of CNFET based fully encoded three inputs LUT in deep submicron (DSM) region for delay, power dissipation and switching energy. Proposed multi-chirality LUT implementation shows significant advantages in delay as well as switching energy.

In general Application Specific Integrated Circuits (ASIC) and Digital Signal Processors (DSP) are usually used for implementing digital filters. As compared to the conventional methods available the speed of computation of digital filter is increased by implementing on Field Programmable Logic Gate Array (FPGA). This paper provides a novel design and implementation of digital filter in FPGA using a high level description tool like Xilinx System Generator. The designed filter with desired specification is analyzed in Simulink environment in MATLAB. A method for implementing IIR filter in FPGA using System Generator is proposed. The Xilinx system generator is used for synthesizing and simulation for FPGA filter analysis. The FPGA shows its high performance in terms of speed, memory, resource management, and power consumption.