Distributed Processor for FPGA-based Superconducting Qubit Control

This paper presents a Field Programmable Gate Array (FPGA) -based platform for integrated multi-axis motion control and motor drive. As the development of FPGA, the integrated high-performance ARM processor on the FPGA has become the direction of FPGA development. This paper chooses the Xilinx Zynq-7020 programmable system-on-chip(SoC) which integrated dual-core ARM CPU and FPGA as a High-performance hardware platform. This platform is suits for the requirements of integrated multi-axis motion control and motor drive well, one ARM CUP completes the multi-axis position loop algorithm, speed loop algorithm and multi-axis trajectory generation, the other completes the human-computer interaction function. 4-axis current loop pipeline control and double sampling double updating current loop algorithm are accomplished by FPGA which can expand the current loop bandwidth and save FPGA logic resources. This platform’s architecture will improve the overall bandwidth of the system, achieve multi-axis synchronization accuracy at nanosecond level which makes position trajectory more accurate.

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two physical limitations: (1) The massive usage of routing multiplexers causes delay and power overheads as compared to ASICs. To reduce their power consumption, FPGAs have to operate at low supply voltage but sacrifice performance because the transistors drive degrade when working voltage decreases. (2) Using volatile memory technology forces FPGAs to lose configurations when powered off and to be reconfigured at each power Resistive Random Access Memories (RRAMs) have strong potentials in overcoming the physical limitations of conventional FPGAs. First of all, RRAMs grant FPGAs non-volatility, enabling FPGAs to be Normally powered off, Instantly powered on. Second, by combining functionality of memory and pass-gate logic in one unique device, RRAMs can greatly reduce area and delay of routing elements. Third, when RRAMs are embedded into datpaths, the performance of circuits can be independent from their working voltage, beyond the limitations of CMOS circuits. However, researches and development of RRAM-based FPGAs are in their infancy. Most of area and performance predictions were achieved without solid circuit-level simulations and sophisticated Computer Aided Design (CAD) tools, causing the predicted improvements to be less convincing. In this thesis,we present high-performance and low-power RRAM-based FPGAs fromtransistorlevel circuit designs to architecture-level optimizations and CAD tools, using theoretical analysis, industrial electrical simulators and novel CAD tools. We believe that this is the first systematic study in the field, covering: From a circuit design perspective, we propose efficient RRAM-based programming circuits and routing multiplexers through both theoretical analysis and electrical simulations. The proposed 4T(ransitor)1R(RAM) programming structure demonstrates significant improvements in programming current, when compared to most popular 2T1R programming structure. 4T1R-based routingmultiplexer designs are proposed by considering various physical design parasitics, such as intrinsic capacitance of RRAMs and wells doping organization. The proposed 4T1R-based multiplexers outperformbest CMOS implementations significantly in area, delay and power at both nominal and near-Vt regime. From a CAD perspective, we develop a generic FPGA architecture exploration tool, FPGASPICE, modeling a full FPGA fabric with SPICE and Verilog netlists. FPGA-SPICE provides different levels of testbenches and techniques to split large SPICE netlists, in order to obtain better trade-off between simulation time and accuracy. FPGA-SPICE can capture area and power characteristics of SRAM-based and RRAM-based FPGAs more accurately than the currently best analyticalmodels. From an architecture perspective, we propose architecture-level optimizations for RRAMbased FPGAs and quantify their minimumrequirements for RRAM devices. Compared to the best SRAM-based FPGAs, an optimized RRAM-based FPGA architecture brings significant reduction in area, delay and power respectively. In particular, RRAM-based FPGAs operating in the near-Vt regime demonstrate a 5x power improvement without delay overhead as compared to optimized SRAM-based FPGA operating at nominal working voltage.

Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.

Chapter 5 - Quantum Algorithms and Methods

Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA’s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

This work contains the analysis of results received after running synthesized quantum circuits for training perceptron neural networks. The training is performed by creating a Grover's algorithm with a custom oracle function. The concept of synthesizing quantum circuits was showcased in the process of generating training circuits for three perceptron topologies, which were designed to test the accuracy of the synthesis process. The test circuits serve to prove that the proposed synthesis approach could be scaled to utilize more complex quantum computing systems and to solve more practical tasks. IBM's 100-qubit cloud quantum simulator was used as the debugging environment. Quantum circuits for described algorithms are generated by the "Naginata" quantum synthesizer, its source code is published and further documented on GitHub along with the code for the provided example algorithms. The article describes the processes behind the algorithm for synthesizing quantum circuits that perform the training process of single-layer perceptrons by finding their weights by filtering all possible input values through a predefined accuracy criterion. Since quantum computing is still in its early development phase, quantum circuits are created mainly by manual placement of logic elements. Implementing quantum algorithms, especially more use-case specific ones, directly on the quantum circuit level could lead to the circuit easily becoming too complex for human comprehension. Quantum Circuit Synthesizer "Naginata" was created to simplify the development and debugging process of quantum algorithms, by adding better clarity to their development process. In our case, better clarity for the development process is achieved by composing functions for commonly used operations performed in the implemented quantum algorithm. The programmer could now implement the quantum algorithm as a set of functions, instead of manually creating a circuit from single logic elements. After this, the synthesizer would handle the task of creating the data for placing logic elements on the circuit. This enables an opportunity of implementing quantum algorithms with higher-level commands. In the scope of this work, parametrically generated generic blocks for frequently used operations such as: the adder, multiplier and digital comparator were created and utilized to form the training circuits. The test results, proved that with the help of the proposed quantum synthesizer, these compositions could be used efficiently as building blocks for implementing quantum algorithms. And by visually comparing sizes of both code and circuit representations of the synthesized circuits, to the code examples used to synthesize these circuits, it is determined that the proposed approach for implementing quantum circuits greatly simplifies the processes of development and debugging a quantum algorithm.

There is no unique way to encode a quantum algorithm into a quantum circuit. With limited qubit counts, connectivities, and coherence times, circuit optimization is essential to make the best use of quantum devices produced over a next decade. We introduce two separate ideas for circuit optimization and combine them in a multi-tiered quantum circuit optimization protocol called AQCEL. The first ingredient is a technique to recognize repeated patterns of quantum gates, opening up the possibility of future hardware optimization. The second ingredient is an approach to reduce circuit complexity by identifying zero- or low-amplitude computational basis states and redundant gates. As a demonstration, AQCEL is deployed on an iterative and effcient quantum algorithm designed to model final state radiation in high energy physics. For this algorithm, our optimization scheme brings a significant reduction in the gate count without losing any accuracy compared to the original circuit. Additionally, we have investigated whether this can be demonstrated on a quantum computer using polynomial resources. Our technique is generic and can be useful for a wide variety of quantum algorithms.

The Arbitrary Waveform Generator (AWG) is an important instrument that is widely used in automatic test equipment, radar system, and other fields for generating complex signals. The increasing demand for waveform's complexity is consisted of repeatable segments and advanced-segments, where each segment or segments group could be repeated multiple times. Those requirements make the existing design, implemented by an address generator, complex. The software defined technology can separate the instruction sequence processing from the Data plane to the Controller where the complex logic is defined by software, which lead to a simplified data plane. This paper proposes a design that will generate complex arbitrary waveform by decoupling the waveform composing logic in address generator out from the data plane as an instruction controller. The controller support instruction sequence defined by segment and a jump instruction, which can implement the repeatable segments and the advanced-segments, respectively. We built an AWG based on this design and made the implementation in a field programmable gate array with a required clock frequency of 125 MHz. The design has a high sampling rate of 4 gigabit samples per second and can generate complex arbitrary waveform consisting of repeatable segments and advanced-segments.

We are developing an arbitrary waveform generator (AWG) to provide enhanced capability for radar applications. The current design accommodates two waveform generators on a single unit for dual frequency operation. The basic architecture of this unit employs a field programmable gate array (FPGA) and a high speed and high precision digital to analog converter (DAC) for direct digital synthesis. This AWG is capable of up to 450 MHz bandwidth with ability for frequency notching. Phase fidelity of better than 1.2/spl deg/ deviation RMS is also achievable. This AWG operates with lower power consumption as compared with other waveform generators, which is advantageous for future spaceborne applications. This will enable radars to return higher precision data, to be reduced in complexity, and to operate in any band without interfering with dedicated bandwidths.

Ternary Content Addressable Memory (TCAM) is widely used in network infrastructure for various search functions. There has been a growing interest in implementing TCAM using reconfigurable hardware such as Field Programmable Gate Array (FPGA). Most of existing FPGA-based TCAM designs are based on brute-force implementations, which result in inefficient on-chip resource usage. As a result, existing designs support only a small TCAM size even with large FPGA devices. They also suffer from significant throughput degradation in implementing a large TCAM, mainly caused by deep priority encoding. This paper presents a scalable random access memory (RAM)-based TCAM architecture aiming for efficient implementation on state-of-the-art FPGAs. We give a formal study on RAM-based TCAM to unveil the ideas and the algorithms behind it. To conquer the timing challenge, we propose a modular architecture consisting of arrays of small-size RAM-based TCAM units. After decoupling the update logic from each unit, the modular architecture allows us to share each update engine among multiple units. This leads to resource saving. The capability of explicit range matching is also offered to avoid range-to-ternary conversion for search functions that require range matching. Implementation on a Xilinx Virtex 7 FPGA shows that our design can support a large TCAM of up to 2.4 Mbits while sustaining high throughput of 150 million packets per second. The resource usage scales linearly with the TCAM size. The architecture is configurable, allowing various performance trade-offs to be exploited. To the best of our knowledge, this is the first FPGA design that implements a TCAM larger than 1 Mbits.

The growth in number of fuzzy logic applications led to the need of finding efficient ways to implement them. The advantage of using Field Programmable Gate Arrays (FPGA) is the ease with which controllers can be re-designed based on requirements without incurring major non recurring engineering (NRE) costs. In this paper, the implementation of a Mamdani Fuzzy Inference System has been demonstrated with the application of a Home Water Sprinkler System. The design of the Home Water Sprinkler System uses two inputs, Temperature and Soil Humidity, to give a single output, Watering Duration. VHDL programming language is used for creating the design in which simulations are carried out to check the functional verification of individual blocks. The design created on VHDL platform was synthesized, verified and implemented using Xilinx Integrated Software Environment (ISE) Version 6.1. The bit stream created is downloaded onto the Xilinx Virtex 2 FPGA which is mounted on a V2MB1000 board. For the verification of FIS, DIP switches and push buttons were used to simulate inputs. The outputs and inputs were displayed on the two seven segment LED displays. The accuracy of the model on FPGA was compared with simulation results obtained using MATLAB & Fuzzy Logic Tool Box. The results obtained from the two models differed with a Root Mean Square (R.M.S.) error of 0.8%.

Fault clearing time is critical to the safety of power system equipment. Most state-of-art distance relays operate at the speed of one cycle or even longer. There are a few sub-cycle algorithms such as half-cycle type Fourier, least error square, traveling wave, and wavelet type methods. This paper utilizes a sub-cycle (phaselet) method for estimation. The algorithm and testing with IEC 61850 Sampled Value and GOOSE communication protocols was discussed in detail in the recently accepted paper by the authors in the IEEE Transactions on Smart Grids [1]. The main focus of this paper is on the hardware implementation of the phaselet method on field programmable gate arrays (FPGAs) to achieve high speed and the hardware-in-the-loop testing. The FPGA implementation of the method helps in parallelizing the algorithm and provides fast computation speed compared to sequential execution on digital signal processor (DSP). The algorithm is implemented on Xilinx Virtex 6 board. The FPGA relay is tested using hardware-in-the-loop simulations with a real time digital simulator (RTDS).

This article presents a new approach to the problem of transforming one quantum state into another. It is shown that an r-qubit superposition |x can be obtained from another r-qubit superposition |y, by using only (2r−1) rotations, each presented by one controlled rotation gate. The quantum superpositions with real amplitudes are considered. The traditional two-stage approach Uy−1Ux:|x→|0⊕r→|y requires twice as many rotations. Here, both transformations to the conventual basis state, Ux: |x→ |0⊕r and Uy: |y→ |0⊕r, use (2r−1) rotations each on two binary planes, and many of these rotations require additional sets of CNOTs to be represented as 1- or 2-qubit-controlled gates. The proposed method is based on the concept of the discrete signal-induced heap transform (DsiHT) which is unitary and generated by a vector and a set of angular equations with given parameters. The quantum analog of this transform is described. The main characteristic of the DsiHT is the path of processing the data. It is shown that there exist such fast paths that allow for effective computing of the DsiHT, which leads to the simple quantum circuits for state preparation and transformation. Examples of such paths are given and quantum circuits for preparation and transformation of 2-, 3-, and 4-qubits are described in detail. CNOT gates are not used, but only controlled gates of elementary rotations around the y-axis. It is shown that the transformation and, in particular, only rotation gates with control qubits are required for initialization of 2-, 3-, and 4-qubits. The quantum circuits are simple and have a recursive form, which makes them easy to implement for arbitrary r-qubit superposition, with r≥2. This approach significantly reduces the complexity of quantum state transformations, paving the way for more efficient quantum algorithms and practical implementations on near-term quantum devices.

Low rank approximation in simulations of quantum algorithms

We present a quantum computing algorithm for fluid flows based on the Carleman-linearization of the Lattice Boltzmann (LB) method. First, we demonstrate the convergence of the classical Carleman procedure at moderate Reynolds numbers, namely, for Kolmogorov-like flows. Then we proceed to formulate the corresponding quantum algorithm, including the quantum circuit layout, and analyze its computational viability. We show that, at least for moderate Reynolds numbers between 10 and 100, the Carleman–LB procedure can be successfully truncated at second order, which is a very encouraging result. We also show that the quantum circuit implementing the single time-step collision operator has a fixed depth, regardless of the number of lattice sites. However, such depth is of the order of ten thousands quantum gates, meaning that quantum advantage over classical computing is not attainable today, but could be achieved in the near or mid-term future. The same goal for the multi-step version remains, however, an open topic for future research.