Don't Repeat Yourself! Coarse-Grained Circuit Deduplication to Accelerate RTL Simulation

This paper introduces GLAAPE, a novel graph learning-assisted neural network model that enables fast, accurate, and transferable estimation of average power in gate-level combinational designs from Register Transfer Level (RTL) simulation. GLAAPE learns to propagate the average toggle rates by effectively embedding the structural information and logical function feature values as vectors on each logic cell of the netlist file. GLAAPE predicts the output toggle rates of combinational logic cells and hence the average power of the benchmark circuits from inputs obtained through RTL simulation without the requirement of gate-level simulation. We evaluate GLAAPE with the commercial gate-level power estimation tool for inference throughput, which is, on average, 15.69X faster. GLAAPE outperforms the commercial RTL Power estimation tool for average power estimation by achieving a mean improvement of 25.28%. We also compare GLAAPE with the state-of-the-art model GRANNITE to predict the output toggle rates to demonstrate the transferability and achieve better accuracy with a mean improvement of 13.95%. We consider a good range of benchmark circuits for analysis, and our experimental results show the generalization and efficacy capability of GLAAPE.

As hardware design complexity increases, efficient Register Transfer Level (RTL) simulation becomes critical for reducing the long runtime of design and verification. Although several parallel RTL simulators have been developed, they often suffer from long compilation times and slow simulation performance, especially for large-scale heterogeneous architectures and deep learning SoC designs that exhibit repetitive and hierarchical structures. These limitations arise because existing simulators fail to effectively map heterogeneous architectures onto CPU-GPU platforms, resulting in underutilized compute resources. In addition, they repeatedly regenerate and recompile redundant code, missing the opportunity to exploit the structural parallelism inherent in deep learning accelerators. To address these challenges, we propose HeteroRTL, a scalable code generation flow that produces hybrid CPU-GPU parallel RTL simulators for heterogeneous deep learning accelerator SoCs. Built on the MLIR infrastructure, HeteroRTL analyzes RTL designs, partitions the simulation between CPU and GPU targets, identifies structural repetition to reduce compilation overhead, and generates efficient simulation executables. Compared to state-of-the-art simulators, HeteroRTL achieves compilation speedups of three to five orders of magnitude and delivers up to 9× and 122× simulation speedups across various designs.

Hardware faults in electronic components are a major concern especially for safety critical systems. In this paper we present an approach, which is based on simulation-based error injection and system prototypes modeled in SystemC. The target of the approach is the realization of an efficient multi-level error effect simulation for the evaluation of the fault-tolerance of a system. We run a combination of fault injection at register transfer level (RTL) and error injection at behavioral level. At RTL, novel non-intrusive fault injectors are used to inject bit flips into the registers of an embedded processor. At the behavioral level, errors are directly injected into the variables of the embedded SW and SW scheduler. This increases the significance of the results because fault masking is avoided at behavioral level. Also more and longer scenarios can be simulated because behavioral level simulation is much faster than RTL simulation. This is illustrated for a case study of an embedded control system with fail-silent recovery scheme.

In the past, research on delay fault testing has been focused on test generation using various delay fault models on full scan gate level netlists. These tests are not very suitable for speed-binning since the confidence that the slowest paths have been covered is low. We have developed a novel methodology with an accompanying tool flow called SpeedGrade that performs path delay fault simulation using an RTL (Register Transfer Level) simulator. This novel method was used to translate the gate level path excitation conditions into higher level of abstraction without loss of accuracy. The higher efficiency of the RTL-based solution allowed for fault grading of functional patterns against the top critical paths in commercial microprocessor designs. The RTL-based approach also had the added benefit of being easier to use for debugging critical paths.

This paper presents a highly resilient boot process design for Ballast, a new RISC- V based multiprocessor system-on-chip (SoC). An open source RISC- V SoC was adapted as a bootstrap processor and customized to meet our requirement for guaranteed chip wake-up. We outline the characteristic challenges of implementing a large program into a read-only memory (ROM) used for booting and propose generally applica-ble workflows to verify the boot process for application specific integrated circuit (ASIC) synthesis. We implemented four distinct boot modes. Two modes that load a software bootloader autonomously from an SD card are implemented for a secure digital input output (SDIO) interface and for a serial peripheral interface (SPI), respectively. Another SDIO based mode allows for direct program execution from external memory, while the last mode is based on usage of a RISC- V debug module. The boot process was verified with instruction set simulation, register transfer level simulation, gate-level simulation and field-programmable gate array prototyping. We received the fabricated ASIC samples and were able to successfully boot the chip via all boot modes on our custom circuit board.

We are developing a 32-bit embedded processor core with soft error detection and recovery mechanisms. Adding a parity bit into pipeline registers makes it possible to detect single event upset in an processor core. Detection of 2-bit and less multiple bit upset and automatic correction of single event upset can be done with single error correction and double error detection code. These soft-error detection/recovery mechanisms cause cost/performance degradation. In this paper, probability of serious calculation failures occurred by SEU in an MIPS R3000 compatible processor core is evaluated. We investigate the probability using register transfer level simulation. The result shows that impacts of SEU to calculation result differ much, when SEU happens in a program counter, an instruction register or register files. Soft error detection/recovery mechanism of an embedded processor core can be selected automatically when permitted soft error rate of an application program is given as a specification.

Today, the most common abstraction level for manual design capture is at the so called register transfer level. At this level, all synchronous registers, latches and the combinational logic between the sequential elements are described in a hardware description language such as Verilog or VHDL. The description is then transformed into logic gate implementations based on a technology specific cell library, a procedure known as logic synthesis. This allows a designer to handle more complex design because detailed manual analysis need not be made at the logic gate level that is more tedious and error prone. Register transfer level is certainly not the only starting point for automated hardware synthesis. The analysis and synthesis of digital circuits are still being pushed toward even higher level of abstraction for manual manipulation. For example, macro block level specification and synthesis has been practiced in some design areas. The register transfer and macro block level design methodologies are part of the architecture and system level techniques to be discussed in this chapter.

CAPE: A cross-layer framework for accurate microprocessor power estimation

This paper presents a new approach for extracting timing information defined in a simulation vector set on register transfer level (RTL) and reusing them in the behavioral specification. Using a VHDL RTL simulation vector set and a VHDL behavioral specification as entry, the timing information is extracted and as well as the specification transformed in a Partial Order based Model (POM). The POM expressing the timing information is then mapped on the specification POM. The result contains the behavioral specification and the RTL timing and is retransformed in a corresponding VHDL specification. Additionally, timing information contained in the specification can be checked using the RTL simulation vectors.

This paper presents a new approach for extracting timing information defined in a simulation vector set on register transfer level (RTL) and reusing them in the behavioral specification. Using a VHDL RTL simulation vector set and a VHDL behavioral specification as entry, the timing information is extracted and as well as the specification transformed in a Partial Order based Model (POM). The POM expressing the timing information is then mapped on the specification POM. The result contains the behavioral specification and the RTL timing and is retransformed in a corresponding VHDL specification. Additionally, timing information contained in the specification can be checked using the RTL simulation vectors.

Fine-Grained Parallel and Distributed Spatial Stochastic Simulation of Biological Reactions

The simulation of aging induced degradation mechanisms is a challenging task during the design of digital systems. Parametrical degradations can be handled most accurately at TCAD level, as the physical models like [1] and [2] can be implemented directly. On the other hand, timing failures caused by such degradations cannot be assessed exactly lower than Register Transfer Level (RTL), where the notion of clock delay and critical paths is introduced. Since System-Level designers have no influence on device level abstractions, this is the lowest level for them to perform optimization. However accurate and realistic timing estimation of different component designs at RTL under aging is problematic as entire components are either too large to be simulated by circuit level simulators like SPICE or the simulations become unacceptably slow. Thus a compact, accurate and efficient model for aging aware timing estimation at RTL is needed to support design technology co-optimization for digital circuits. This work evaluates a new RTL timing model concept with respect to accuracy and capability of separating design- and stress related impacts on aging, by applying different stress scenarios at RTL to a selection of ISCAS89 Benchmark circuits. The results indicate that the modeled timing estimations are sufficiently accurate, with average RMS of 1.13% for the deviation between circuit-level and the model. Results also demonstrate that the separation of design- and stress related aging impacts provided by the approach is adequate with average RMS of 2.06% respectively. This is a significant step towards a black box RTL timing model for aging assessment.

Background: In recent years, the rising demand for high-performance radar systems in aeronautics, astronautics, national defense, and civil communication has driven the widespread application of phased-array technology. The design of beam controllers, the core of phased-array systems, faces many challenges. Traditional implementation schemes are usually based on application-specific integrated circuits (ASIC) or discrete components, which have a long development cycle, poor flexibility, and limited adaptability. Field-programmable gate arrays (FPGA), with their high parallelism, reconfigurability, and powerful signal processing capabilities, offer a new way to implement phased-array control systems. But FPGA design has traditionally relied on register transfer level (RTL) description, which is inefficient and struggles to keep up with the rapid iteration of complex algorithms. With the development of high-level synthesis (HLS) technology, it has become possible to develop FPGAs using high-level languages such as C/C++. However, improving development efficiency while ensuring hardware performance remains a key issue in the design of phased-array beam controllers. Materials and Methods: This study employs an HLS - RTL co - design method to build a phased - array beam controller. This approach combines the strengths of HLS's efficient algorithm implementation and RTL's precise hardware interface control. The system architecture consists of three parts: the host - machine control layer, FPGA processing layer, and phase - control output layer. In the FPGA processing layer, the core beam - forming algorithm is implemented via HLS. Based on phased - array principles, this algorithm converts target angles to wave vectors and calculates phase - compensation values for each element in an 8×8 array. Pipelining and parallel processing techniques are used in the HLS design to optimize algorithm throughput and latency. The phase - control output layer, designed with RTL, repackages 64 calculated phase values and distributes them to 16 physical phase - shifter chips. Each phase - shifter manages four elements and receives control data through an SPI interface. Results: The proposed FPGA-based phased-array beam controller design in this paper has successfully achieved high - speed, high - precision beam control. By using the HLS - RTL co - design method, it has solved the problem of low algorithm implementation efficiency in traditional FPGA development and ensured the high performance and reliability of hardware interfaces. Experimental results indicate that the system meets or surpasses design targets on key performance indicators. Its end - to - end latency is kept within 130μs, it supports an angle update rate of over 5,000 times per second, and can satisfy the requirements for tracking highly dynamic targets in practical applications. Conclusion: The major contributions of this research are as follows: presenting an HLS - RTL co - design methodology for complex FPGA system development; designing an efficient phased - array beam - forming algorithm and its hardware implementation; and developing a flexible and scalable phased - array control system architecture that supports different array configurations. These findings are highly significant for beamforming technologies in phased - array radar and 5G communication systems, as well as for other FPGA applications requiring high - speed signal processing.

Given the complexity of SoC development in the nanotechnology, it has become critical to fully validate the system performance at the early stage of the SoC design flow. This chapter describes the tools and methods for evaluating the overall SoC interconnect performance, for which the commercial solutions are not yet available. The proposed methodology is based on SystemC simulation using a generic IP Traffic Generator (IPTG) and a powerful monitoring mechanism called SysProbe, which are applicable all through the SoC analysis flow ranging from the transactional to register transfer level (RTL) simulations. Such Traffic Generators model the system IPs and the system traffic dependency with a refinement flow, while real slaves or targets are used to generate the correct latency. The SoC architecture is modeled either at the transactional or RTL level according to the requirements of development costs, simulation speed and precision. SysProbe provides the results of the architectural analysis to SoC architects.

Many different forms of simulation can be used for the analysis of large digital integrated circuit designs at the various stages of the design process. They may be classified as Behavioral (also called algorithmic or functional) simulators, Register Transfer Level (RTL) simulators, Gate Level Logic simulators, timing simulators, and circuit simulators, as illustrated in Fig.1.1.