Double-patterning friendly grid-based detailed routing with online conflict resolution

Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, un-correlated distributions of linewidth on a chip, resulting in a ‘bimodal’ linewidth distribution and an increase in performance variation. [13] suggested that new physical design mechanisms could reduce harmful covariance terms that contribute to this performance variation. In this paper, we propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standard-cell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts. Our second contribution is an ILP-based maximization of ‘alternate’ mask coloring of instances in timing-critical paths, to minimize harmful covari-ance and performance variation. Third, we propose a dynamic programming-based detailed placement algorithm that solves mask coloring conflicts and can be used to ensure “double patterning correctness” after placement or even after detailed routing, while minimizing the displacement of timing-critical cells with manageable ECO impact. With a 45nm library and open-source design testcases, our timing-aware recoloring and placement optimizations together achieve up to 232ps (resp. 36.22ns) reduction in worst (resp. total) negative slack, and 78% (resp. 65%) reduction in worst (resp. total) negative slack variation.

Double Patterning Lithography (DPL) for next-generation wafer exposure is placing greater demands on the requirements for pattern placement accuracy on photomasks: the DPL mask pair must now meet the pattern placement specifications that a single mask was required to meet in previous generations. As a result, each mask in the mask pair must individually conform to much tighter mask registration specs. Minimizing all sources of systematic overlay error has become critical. In addition, the mask-to-mask overlay between the two masks comprising the DPL pair must be measured-a methodology shift from the current practice of referencing mask registration error only to design data. Characterizing mask-to-mask overlay error requires the ability to measure pattern placement errors using in-die structures on reticle pairs. Today's analysis methods do not allow for comparison of registration maps based on different site locations. This gap has created a lack of information about the true overlay impact of mask-to-mask registration errors on masks with few or no common features. A new mask-to-mask overlay analysis method is demonstrated that provides new flexibility for mask-to-mask comparison. This new method enables mask manufacturers to meet fab requirements for DPL, and it enables semiconductor manufacturers to verify if overlay deviations are within acceptable limits.

As the technology nodes scale down to sub-22 nm, double patterning lithography has been considered as a practical solution for layout manufacturing. Compared with litho-etch-litho-etch, self-aligned double patterning (SADP) has better overlay control. To have a better SADP layout decomposability of routing patterns, we consider SADP during detailed routing stage. Two major types of SADP processes are considered: 1) spacer-is-dielectric type and 2) spacer-is-metal type. Different from previous works, the idea of color preassignment is adopted for SADP-aware detailed routing. An elegant graph model is proposed to capture both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules in detailed routing. We apply a negotiated congestion based rip-up and reroute scheme to achieve better routability while maintaining SADP design rules. Compared with other state-of-the-art academic works, our approach does not produce any side overlay error and no SADP design rules violation is reported. Meanwhile, a better solution in terms of total wirelength, routability, and runtime is achieved.

As integrated circuit technology nodes continue to shrink, dense via distribution becomes a severe challenge, requiring multiple masks to avoid spacing violations in via layers. Meanwhile, the directed self-assembly (DSA) technique shows a great promise in via printing by employing feasible guiding templates. Combining DSA with double patterning lithography can significantly reduce the number of masks for via layers. In this paper, we propose a detailed routing algorithm considering DSA with DPL based on a conflict and compatibility graph model. A net planning algorithm is developed to reduce via-dense areas and determines a prerouting nets order, while the graph model is employed to capture the feature of DSA and DPL to better guide detailed routing. Besides, DSA grouping is performed for critical vias during detailed routing to avoid attracting more vias inserted in surrounding grids to reduce via-spacing violations. Experimental results demonstrate that our routing algorithm can effectively minimize the number of via spacing violations, with an even smaller total via count.

In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achieve high quality solution for DPL-unfriendly designs, due to complex 2D patterns in lower metal layers. Therefore, DPL-friendliness is needed at routing stage [3]. Another key yield improvement technique is redundant via insertion [4] [5]. However, this would increase the complexity in DPL-compliance. To make designs manufacturable in DPL, we should not insert a redundant via if it results in coloring conflict. This paper is the first work to consider DPL and redundant via together. We have developed two algorithms, post-routing DPL-aware insertion and DPL-friendly routing with redundant via consideration to take into account redundant via DPL-compliance. Experimental results show that, compared to a DPL-aware optimization flow without redundant via consideration, we can improve insertion rate by 43% while still achieving zero coloring conflicts. Moreover, we can reduce the number of vias and stitches by 9% and 17% respectively.

Double patterning lithography (DPL) is the most likely manufacturing process for sub-32nm technology nodes; however, there are several double patterning strategies each of which exhibits different layout decomposition challenges. Self-aligned double patterning (SADP) has attracted much interest due to its robustness against overlay errors, but SADP compliance depends strongly on the characteristics of the individual masks generated during the layout decomposition. This work establishes SADP decomposition requirements and proposes a litho-friendly layout decomposition method. First, we explain the main parameters that limit printability of SADP decomposed layouts. In-silico experiments indicate that layout patterns which are printed by the Trim mask may experience the highest levels of image transfer sensitivity. For that reason, these patterns should be assisted by sidewalls of spacer patterns which are robustly printed. Next, we present an ILP-based decomposition method which avoids decomposition conflicts and sensitive Trim edges simultaneously. Our experiments on several industrial designs reveal that the proposed method decreases the total length of sensitive Trim patterns and consequently reduces the overall edge placement error significantly.

Stochastic optimal control for aircraft conflict resolution under wind uncertainty

Double patterning lithography is extensively used to increase the half-pitch resolution. If there is no enough space to insert a stitch for the un-decomposable pattern, a native conflict is generated. A layout with native conflicts will result in layout modification. The current researches focus on reducing the numbers of stitches and native conflicts in the post-layout or detailed routing stages. In this paper, we propose a track routing algorithm to avoid native conflicts and predict the traces of detailed routing. Experimental results show that the proposed method not only minimizes the number of native conflicts significantly, but also reduces wirelength.

A method for conflict detection and resolution based on the parameterization of the aircraft intents is presented. The method is also based on the use of predefined trajectory patterns, which are in fact flight intents; these patterns include standard airline procedures and air traffic control regulations. The conflict resolution problem is formulated as a parametric optimization problem subject to constraints; the optimality criterium is defined so that the deviation from the intended (preferred) trajectories in the lateral profile is minimized. The resolution trajectory patterns take into account changes of the nominal waypoints (vectoring) and changes of the aircraft speeds. The method is applied to the case of multiple conflicts among commercial transport aircraft in converging traffic in the terminal area; different scenarios are considered, which include locked aircraft, that is, aircraft whose trajectories are known and fixed. The conflict detection and resolution algorithm relies on a kinetic trajectory predictor (nonlinear point-mass model with variable mass), which is accurate, flexible, and transparent, and provides the high-fidelity prediction required in the analysis of the demanding terminal area traffic. The cost of the global conflict resolution process is assessed, in terms of extra distance traveled, extra flight time, and extra fuel consumed for each aircraft.

While double patterning lithography (DPL) is still in active development, triple or even quadruple patterning has recently been proposed for the next technology node. In this paper, we propose a pairwise coloring (PWC) method to tackle the layout decomposition problem for general multiple patterning lithography (MPL). The main idea is to reduce the problem to sets of concurrent bi-coloring problems. The overall solution is refined iteratively by applying a bi-coloring method for pairs of color sets per pass. One obvious advantage of this approach is that the existing DPL techniques can be reused seamlessly. Any improvement of them can directly benefit to the MPL counterpart. Moreover, we observe that with the help of the SPQR-tree graph division method, each pass can be fulfilled in nearly linear time. In addition, to prevent the solution getting stuck in the local minima, a randomized initialization strategy is incorporated. The PWC method is executed certain number of times with different randomized initial solutions, out of which the best solution is selected as output. We have implemented our method for particular triple patterning lithography (TPL). The experimental results show that compared with two recently published methods for TPL, our method can reduce the number of conflicts up to 33.2% and 44.9% respectively.

The pilot- and controller-in-the-loop simulation described in this paper demonstrates the potential benefits of a near-term trajectory-based operations concept with datalink communications. Near-term operations with datalink are characterized by a fleet of which not all aircraft are equipped with datalink communications (i.e., mixed equipage). The objectives of this simulation were to continue to develop capabilities such as the conflict resolution algorithm, as well as evaluate new capabilities and concepts such as tactical conflict detection and trajectory-based weather avoidance with feedback from experienced pilots and controllers. Conflict resolutions and tactical conflict detections were compared to controller actions. The direction of the conflict resolution maneuver advised by the algorithm agreed with controller actions 79% of the time when both chose to apply the same type of resolution maneuver to the same aircraft. Comparing controller actions to conflicts detected by the tactical conflict detection function revealed no missed alerts and a false alert rate of 11%. Trajectory-based weather avoidance functions received high ratings from the controllers for usefulness and ease of use. In particular, controllers noted weather avoidance reroutes originating from a simulated traffic management coordinator position alleviated their concerns about potentially disrupting traffic flow management plans, thus expediting the issuance of the reroutes.

China has been gradually relaxing its ban on the use of low-altitude airspace across the country. To guarantee the high reliability of air traffic management (ATM), conflict detection and conflict resolution (CDR) approaches are indispensable to maintain safe separation between neighbouring small fixed-wing aircraft. In this study, we analyse a temporal and spatial integrated strategy for safety assessment purposes in opening the low-altitude urban airspace of Chinese pilot cities. First, we present a detailed mathematical description of the proposed algorithms based on a spatial grid partitioning system (SGPS). For our system, a conflict detection (CD) algorithm is designed to determine if two trajectories pass through the same grid space within overlapping time windows. A conflict resolution (CR) algorithm integrates a proposed time scheduling-based technique (TST) and vertical change-based technique (VCT), which operate under predetermined basic principles. Then, based on our novel CDR algorithms, a causal model is constructed in graphical modelling and analysis software (GMAS) to generate a state space that can provide a global perspective on scenario dynamics and better understanding of induced conflict occurrences. Finally, simulation results demonstrate that the proposed approach is practical and efficient.

Given a set of IO buffers and bump balls with the capacity constraints between bump balls, an O(n2) IO assignment and RDL routing algorithm is proposed to assign all the IO connections and minimize the total wirelength with satisfying the capacity constraints and guarantee 100% routability if the capacity constraint is permitted, where n is the number of bump balls in a flip-chip design. Compared with the combination of the greedy IO assignment and our RDL routing, our IO assignment reduces the global wirelength by 7.6% after global routing and improves the routability by 8.8% after detailed routing on the average. Compared with the combination of our IO assignment, the single-layer BGA global router[8] and our detailed routing phase, our RDL routing reduces the global wirelength by 15.9% after global routing and improve the routability by 10.6% after detailed routing on the average for some tested circuits in reasonable CPU time.

Double patterning technology (DPT) is emerging as the dominant technology to achieve the 32-nm node and beyond. Two challenges faced by DPT are layout decomposition and overlay error. To handle the challenges, some effort has been made to consider DPT during detailed routing. In this paper, we propose two enhancing techniques for DPT-friendly detailed routing: lazy color decision and last conflict segment recording. Experiments show that our techniques are able to reduce the number of stitches by 15~20% with 4% increase in running time.

Conflict is inevitable to take place in collaborative design, and conflict resolution plays an important part in complex product collaborative design systems. Firstly, a mathematic description model in collaborative design considering resource conflict, process conflict and design conflict is given, and the mathematic model expresses the origin of conflict and shows that conflict resolution is a multiobjective planning problem. Next, a conflict resolution algorithm considering design objective optimization is presented, and fuzzy value and fuzzy grade are applied in the algorithm. Depending on both considering design variables having fundamental influences on its design objectives and the cost of conflict resolution, the algorithm can improve the quality and efficiency of conflict resolution. Finally, an example of single cylindrical gear reducer is used to show the validity of the algorithm.