Dual path instruction processing

Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditional code placement techniques have less benefit in the presence of a trace cache that alters the placement of instructions in the instruction cache. Moreover, as pipelines have become deeper to accommodate increasing clock rates, branch misprediction penalties have become a significant impediment to performance. We evaluate pattern history table partitioning, a feedback directed code placement technique that explicitly places conditional branches so that they are less likely to interfere destructively with one another in branch prediction tables. On SPEC CPU benchmarks running on an Intel Pentium 4, branch mispredictions are reduced by up to 22% and 3.5% on average. This reduction yields a speedup of up to 16.0% and 4.5% on average. By contrast, branch alignment, a previous code placement technique, yields only up to a 4.7% speedup and less than 1% on average.

Current processors exploit out-of-order execution and branch prediction to improve instruction level parallelism. When a branch prediction is wrong, processors flush the pipeline and squash all the speculative work. However, control-flow independent instructions compute the same results when they re-enter the pipeline down the correct path. If these instructions are not squashed, branch misprediction penalty can significantly be reduced. In this paper we present a novel mechanism that detects control-flow independent instructions, executes them before the branch is resolved, and avoids their re-execution in the case of a branch misprediction. The mechanism can detect and exploit control-flow independence even for instructions that are far away from the corresponding branch and even out of the instruction window. Performance figures show that the proposed mechanism can exploit control-flow independence for nearly 50% of the mispredicted branches, which results in a performance improvement that ranges from 14% to 17,8% for realistic configurations of forthcoming microprocessors.

Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically required to buffer and process such instruction window sizes significantly degrade the cycle time. This paper proposes a novel checkpoint processing and recovery (CPR) microarchitecture, and shows how to implement a large instruction window processor without requiring large structures thus permitting a high clock frequency.We focus on four critical aspects of a microarchitecture: (1) scheduling instructions, (2) recovering from branch mispredicts, (3) buffering a large number of stores and forwarding data from stores to any dependent load, and (4) reclaiming physical registers. While scheduling window size is important, we show the performance of large instruction windows to be more sensitive to the other three design issues. Our CPR proposal incorporates novel microarchitectural schemes for addressing these design issues---a selective checkpoint mechanism for recovering from mispredicts, a hierarchical store queue organization for fast store-load forwarding, and an effective algorithm for aggressive physical register reclamation. Our proposals allow a processor to realize performance gains due to instruction windows of thousands of instructions without requiring large cycle-critical hardware structures.

Instruction level parallelism has become more and more important in today's microprocessor design. These microprocessors have multiple function units, which can execute more than one instruction at the same machine cycle to enhance the uniprocessor performance. Since the function units are usually pipelined in such microprocessors, branch misprediction penalty tremendously degrades the CPU performance. In order to reduce the branch misprediction penalty, predicated operation has been introduced in such microprocessor design as one of the new architectural features, which allows compilers to remove branches from programs. The compiler converts programs with conditional branch to predicated code on these microprocessors with predicate operation support by using comparison instructions to set up Boolean predicates corresponding to branch conditions. Instructions previously guarded by a branch are guarded by a predicate. Predicates guard execution by either executing or nullifying the instruction according to the predicate's value. In this report we present an algorithm to convert a control flow graph into predicated code. The algorithm shown in this report not only minimizes the number of predicates used for basic blocks in the control flow, but also moves the predicate assignments as early as possible to relax dependence constrains introduced by the if-conversion for the later phases of compiler such as the instruction scheduler and register allocator. The algorithm doesn't simply assign the predicate associated with a basic block to the instructions in the basic block. It assigns the predicate associated with the “farthest” dominator basic block to an instruction, to which the instruction can be speculatively moved without introducing compensation code in the instruction scheduling. An optimization algorithm for if-converted code is discussed in the report as well. The algorithm is specially developed for predicated code optimization, which is different from the traditional optimizations. Common subexpression hoisting and sinking employs flow analysis, that extends the traditional common subexpression elimination technique. This algorithm requires traditional flow analysis information such as dominate and post-dominate relationship. Actually, the algorithm can be generalized on predicated code after if-conversion, which is particularly beneficial for single assignment DAG representation of the predicated code.

The modelling and management of temporal constraints over business processes has received some attention in the past years. Recently, we have introduced and discussed the concept of for workflow schemata modelling real world business processes: controllability, originally introduced in the AI community for temporal constraint networks, refers to the capability of executing a workflow for all possible durations of all tasks. In this paper, we first extend the execution strategy proposed by Morris, Muscettola and Vidal in the context of temporal constraint networks, to deal with the execution of business processes in a more suitable way. Then, we discuss and propose a new algorithm to deal with the (dynamic) controllability of an overall workflow schema, where several, possibly disjoint, execution paths are possible, due to the presence of alternative paths in the workflow schema. We show that the presence of several controllable alternative execution paths in a workflow schema does not guarantee that the overall workflow schema is controllable.

Although graph coloring is widely recognized as an effective technique for global register allocation, the overhead can be quite high, not only in execution time but also in memory, as the size of the interference graph needed in coloring can become quite large. In this paper, we present an algorithm based upon a result by R. Tarjan regarding the colorability of graphs which are decomposable using clique separators, that improves on the overhead of coloring. The algorithm first partitions program code into code segments using the notion of clique separators. The interference graphs for the code partitions are next constructed one at a time and colored independently. The colorings for the partitions are combined to obtain a register allocation for the program code. The technique presented is both efficient in space and time because the graph for only a single code segment needs to be constructed and colored at any given point in time. The partitioning of a graph using clique separators increases the likelihood of obtaining a coloring without spilling and hence an efficient allocation of registers for the program. For straight line code an optimal allocation for the entire program code can be obtained from optimal allocations for individual code segments. In the presence of branches, optimal allocation along one execution path and a near optimal allocation along alternative paths can be potentially obtained. Since the algorithm is highly efficient, it eliminates the need for a local register allocation phase.

Most computer applications are published with bugs, whose reproducibility is strictly dependent on the availability of detailed information about the real usage of the application. Unfortunately, this data collection process raises severe privacy issues, as error reports are very likely to include personal information. This represents a strong disincentive for users to submit error reports, hampering the software maintenance process. In this work we address the issue of how to design data obfuscation mechanisms aimed at anonymizing the error reports generated by faulty applications, without compromising the bug reproducibility. The solution presented in this paper, MultiPathPrivacy, is based on an idea which is, to the best our knowledge, still unexplored in literature: maximizing the achievable degree of obfuscation by exploiting the presence of multiple execution paths leading to the manifestation of the same bug. MultiPathPrivacy relies on an off-line reach ability analysis phase, based on symbolic execution techniques, which is aimed at identifying not only the set of alternative execution paths leading to the execution of the code block where the bug manifested, but also to determine the symbolic constraints on the user inputs that are necessary to generate such execution paths. By exploiting the presence of disjoint sets of alternative user inputs/execution paths leading to the manifestation of the same bug, MultiPathPrivacy allows achieving striking improvements of the anonymization quality when compared to state of the art solutions. Via an experimental study, based both on a real, privacy-sensitive application and on publicly available software repositories, we show that MultiPathPrivacy can achieve up to 87% reduction of the amount of user input information leaked by the error report, evaluated in terms of bits of information revealed, and percentage of residual non-anonymized input.

As Out-of-Order (OOO) cores scale to very large instruction windows to extract higher instruction level parallelism (ILP), the cost of mis-speculation increases tremendously. Branch predictors sitting at the head of the pipeline are a significant contributor to the speculatively executed code. It is critical to limit the execution time down the wrong path for the sake of performance and energy efficiency. Architects continue to increase the branch predictor sizes and improve the prediction algorithms to mitigate the increasing cost of the mis-speculations. Unfortunately, there still exists branches whose outcomes are predominantly data dependent, and that significantly contribute to the overall mispredictions. This work is the first to characterize data dependent branches at a scale spanning 100+ workloads drawn from several application categories and establish a clear motivation to address them. We find that branches which have only one load instruction feeding them and only simple operations to compute the branch direction from the load value are responsible for a significant fraction of the overall mispredictions. We call such branches Direct Data Dependent (3D) branches. We develop a family of synergistic techniques to avoid mispredictions from such 3D-branches. We describe 3D-Branch Overrider, our novel branch overriding technique that operates in the front-end of the pipeline to minimize the branch misprediction penalties. On a modern Icelake-like OOO core equipped with the state-of-the-art branch predictor, we find that our technique provides a 12.7% reduction in branch mispredictions resulting in 3.1% Instructions Per Cycle (IPC) gain while needing just 5.7KB in additional storage. As future cores become wider and deeper, we show that the gains from 3D-Branch Overrider nicely increases, even if the size of the underlying branch predictor is aggressively scaled.

Modern embedded processors use small and simple branch predictors to improve performance. Using complex and accurate branch predictors, while desirable, is not possible as such predictors impose high power and area overhead which is not affordable in an embedded processor. As a result, for some applications, misprediction rate can be high. Such mispredictions result in energy wasted down the mispredicted path. We introduce area-aware and low-complexity pipeline gating mechanisms to reduce energy lost to possible branch mispredictions in embedded processors. We show that by using a simple gating mechanism which comes with 33-bit area overhead, on average, we can reduce the number of executed instructions by 17% (max: 30%) while paying a negligible performance cost (average 1.1%).KeywordsArea OverheadEmbed ProcessorConfidence EstimationWaste ActivityBranch InstructionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Dynamic symbolic execution or concolic testing has been proposed recently to effectively generate test inputs for real-world programs. Unfortunately, dynamic symbolic execution techniques do not scale well for large realistic programs, because often the number of feasible execution paths of a program increases exponentially with the increase in the length of an execution path. We believe that programmers usually have a good understanding of programs they write and could help concolic testing to guide path exploration effectively so that concolic testing can achieve the desired testing goal quickly. In this paper, we propose a simple annotation mechanism, called Guide SE, that enables a programmer to guide concolic testing by annotating the program under test. We have currently identified three mechanisms for providing these annotations: control annotations, equivalence annotations, and data annotations. Controls annotations allow a programmer to specify the paths of interest using regular expressions. Equivalence annotations enable a programmer to prune paths that result in user defined equivalent states. Data annotations allow a programmer to abstract portions of the program under test and to explore the reduced path space of the abstract program.

The paper presents the recent approach to SFC development in CPDev engineering environment. A simple sequential tank filling control is described for reference. Using the example, a new SFC editor is presented, together with special function blocks for action management. The development process covers creating a graphical operator HMI which interacts with the SFC control part. It is also shown how the project may be simulated to detect errors. A new scalable runtime supporting large projects with multiple steps and execution paths is presented. The runtime is able to process multiple tasks at a time, so the control and HMI part are executed in parallel at the same machine sharing common variables.

Dynamic symbolic execution (DSE) has been proposed to effectively generate test inputs for real-world programs. Unfortunately, DSE techniques do not scale well for large realistic programs, because often the number of feasible execution paths of a program increases exponentially with the increase in the length of an execution path. In this paper, we propose MultiSE, a new technique for merging states incrementally during symbolic execution, without using auxiliary variables. The key idea of MultiSE is based on an alternative representation of the state, where we map each variable, including the program counter, to a set of guarded symbolic expressions called a value summary. MultiSE has several advantages over conventional DSE and conventional state merging techniques: value summaries enable sharing of symbolic expressions and path constraints along multiple paths and thus avoid redundant execution. MultiSE does not introduce auxiliary symbolic variables, which enables it to 1) make progress even when merging values not supported by the constraint solver, 2) avoid expensive constraint solver calls when resolving function calls and jumps, and 3) carry out most operations concretely. Moreover, MultiSE updates value summaries incrementally at every assignment instruction, which makes it unnecessary to identify the join points and to keep track of variables to merge at join points. We have implemented MultiSE for JavaScript programs in a publicly available open-source tool. Our evaluation of MultiSE on several programs shows that 1) value summaries are an eective technique to take advantage of the sharing of value along multiple execution path, that 2) MultiSE can run significantly faster than traditional dynamic symbolic execution and, 3) MultiSE saves a substantial number of state merges compared to conventional state-merging techniques.

While the wireless local area network (WLAN) has been the most common technology for static indoor wireless services, its applications has limited performance in seamless mobile services because of its inherent static service transaction mechanisms. In this paper, we propose a mobility provisioning handoff method called dual cross-linking method to support seamless services in WLAN. A mobile node (MN) has two wireless interfaces and access points (APs) are controlled by a mobility management (MM) agent. In the area where the service areas of two adjacent APs are overlapped, one wireless interface is used to maintain the wireless services while the other interface searches for a next available AP. After finding a new AP, MN forms dual communication path from the MM to the MN so that the MN is ready to move to a newly found AP service area without service loss. Once the MN is moved to a new AP area, the first interface is disconnected leaving only one interface connection. It was proved that the proposed method can effectively reduce the handoff delay and packet loss through the analysis.

Statistical bug isolation techniques attempt to capture a correlation of various program features (like predicates and profiled paths) for debugging. These techniques collect profile data for multiple executions, both with successful and faulty runs, and propose using various statistical tests to capture this correlation. In this paper, we explore the utility of program phases, a concept which is primarily used by computer architects to speed up architectural simulations, for statistical bug isolation. Program phases represent sets of execution intervals in a program's execution where the rates of architectural statistics like branch mispredictions, CPU/Memory usage and cache misses remain almost the same. We found multiple scenarios where coupling program phases with predicates achieves higher accuracy to bug localization than when predicates are used alone. We demonstrate the use of program phases for bug isolation by presenting experimental results and concrete case studies on medium-size programs, showing an improved ranking of the program points that are critical to debugging over when program phases are not used.

Simultaneous Speculation Scheduling ( S 3 ) is a combined compiler and architecture technique to control multiple path execution. It can be used for dual path branch speculation in case of unpredictable branches and for multiple path speculative execution of loop iterations in case of loop-carried dependences that make parallel execution otherwise impossible. We apply S 3 In situations where purely static techniques cannot prove data independence. S 3 can be seen as a cost-effective alternative to purely dynamic speculation techniques. We explain the S 3 technique and discuss the requirements on possible target architectures. We further compare S 3 to other speculation techniques.