Dynamic Built-In Redundancy Analysis for Memory Repair

The test cost and yield improvement of embedded memories have become very important as memory capacity and density have grown. For embedded memories, built-in redundancy analysis (BIRA) is widely used to improve yield by replacing faulty cells with a 2-D redundancy architecture. However, the most important factor in BIRA is the reduction of hardware overhead while keeping optimal repair rate. Most BIRA approaches require extra hardware overhead in order to store and analyze faults in the memory. These approaches do not utilize spare memories during the redundancy analysis (RA) procedure. However, the proposed BIRA minimizes area overhead by utilizing a part of the spare memory as an address mapping table (AMT). Since storing the faulty memory addresses take most of the extra hardware overhead, the reduced logical addresses produced by the AMT are used to reduce the extra hardware overhead. In addition, the reduced addresses are stored in content-addressable memories (CAMs) and used in the RA procedure. The proposed BIRA can achieve an optimal repair rate by using an exhaustive search RA algorithm. The proposed RA algorithm compares the repair solution candidates with all the fault addresses stored in the proposed CAMs to guarantee an exhaustive search. The experimental results show that the proposed BIRA requires a smaller area overhead than that of the previous state-of-the-art BIRA with an optimal repair rate.

With the growth of memory capacity and density, test cost and yield improvement are becoming more important. In the case of embedded memories for systems-on-a-chip (SOC), built-in redundancy analysis (BIRA) is widely used as a solution to solve quality and yield issues by replacing faulty cells with extra good cells. However, previous BIRA approaches focused mainly on embedded memories rather than commodity memories. Many BIRA approaches require extra hardware overhead to achieve the optimal repair rate, which means that 100% of solution detection is guaranteed for intrinsically repairable dies, or they suffer a loss of repair rate to minimize the hardware overhead. In order to achieve both low area overhead and optimal repair rate, a novel BIRA approach is proposed and it builds a line-based searching tree. The proposed BIRA minimizes the storage capacity requirements to store faulty address information by dropping all unnecessary faulty addresses for inherently repairable die. The proposed BIRA analyzes redundancies quickly and efficiently with optimal repair rate by using a selected fail count comparison algorithm. Experimental results show that the proposed BIRA achieves optimal repair rate, fast analysis speed, and nearly optimal repair solutions with a relatively small area overhead.

Test cost and yield enhancements are the vital parameters as the memory capacity and density increase. Built-in redundancy analysis (BIRA) is primarily used for incorporated memories to resolve yield and quality by replacing faulty cells with available cells. Various BIRA approaches need different area overheads to achieve optimal repairs. It is not easy to get low area overhead along with optimal repair rate. A novel BIRA method is proposed that requires less storage for storing faulty address information by deleting the data of unimportant faulty cell addresses. The proposed BIRA examines redundant spares quickly to achieve optimal repair rate. Simulation results show that the proposed BIRA does the spare allocations efficiently.

With advancements in manufacturing and design technology, memory integration density has improved. However, as integration density increases, the cost of testing and repairing memory has also risen, posing a significant challenge in memory production. To address this challenge, built-in self-repair (BISR) has been proposed. Traditional built-in redundancy analysis (BIRAs) performs limited analysis of faults during the fault collection process, resulting in a significant delay in generating a repair solution after the test sequence is completed. This inefficiency arises from the time required to repair the memory posttest. This article proposes a new fast and optimal BIRA using smart potential case collection. The proposed BIRA conducts a detailed analysis of detected faults during the test process. Using this novel fault collection results, a potential case is generated. This is a repair case that can repair the memory with a high probability and is generated immediately after the test sequence ends. If the memory cannot be repaired by the potential case, an exhaustive search is conducted for the faults requiring further analysis to generate an optimal repair solution. Compared to previous studies, the proposed BIRA demonstrates extremely low analysis time with an optimal repair rate.

Optimized counting threshold Built-in redundancy analysis for memories

In system on chip (SOC) design, memory occupies a large area, if any defects in the memory that will affect the SOC’s total yield. To avoid this, spare rows and columns are added to the memory. When the fault cells need to be operated, spares rows/columns will be used instead of faulty cells using Built-in self-repair (BISR) logic. Repairing logic includes either row repair/column repair or a combination of both. In this paper, we propose two methods, one is on the memory built-in self-test (BIST) for checking the memory array circuit. In the second method, an optimized BISR is employed to repair the faulty memory cells based upon the Built-in redundancy analysis. In the BIST method, our proposed method injects the faults into memory by using two fault injection techniques called saboteurs and mutants with optimized test pattern logic. After the injection of the faults in the memory cell, the fault memory is repaired with the proposed counting threshold algorithm for the BISR scheme. Simulation and synthesis results are obtained using Mentor Graphics and Xilinx ISE Design Suite. From our obtained results it can be inferred that various performance measures like power, area, and timing details are reduced in the proposed methods when compared with the existing exhaustive methods. And this proves that the performance of the overall process is found to be enhanced. Thereby yield can also be enhanced with minimum time to market.

With the development of memory density, the probability of occurring faults in memory also increases. To overcome this problem, many built-in redundancy analysis (BIRA) algorithms have been proposed to repair the faults using redundancy cells in memory. Most of previous algorithms have focused on single memory block with local spare cell architecture. However, many memories in system consist of multiple local memory blocks with various spare cell architectures. Thus, the proposed algorithm is based on not only local spare cell but also various spare cell architectures. The experimental results show that repair rate, and hardware overhead of BIRA with various spare cell architectures in multiple memory blocks. The proposed algorithm is practical solution for multiple memory blocks which have global spare cell and common spare cell.

최근의 시스템 온 칩 (SoC) 설계 기술의 발전에 따라, 수백개의 임베디드 메모리 코어들이 칩의 대부분의 면적을 차지하고 있다. 그러므로 시스템 온 칩의 수율은 임베디드 메모리 코어들의 수율에 따라 결정된다고 볼 수 있다. 최적의 수리 효율을 가지는 built-in self repair (BISR)을 모든 메모리들이 가지고 있게 된다면 면적의 부담이 너무 크다. 본 논문에서는 이와 같은 면적의 부담을 줄이기 위하여 메모리들을 그룹화 한 후에 비트맵 메모리를 공유하여 면적 부담을 크게 줄이는 방법을 제안한다. 제안하는 비트맵 메모리 공유방법은 built-in redundancy analysis (BIRA)의 면적을 크게 줄일 수 있다. 실험결과를 통해서 보면 제안하는 방법이 면적 부담을 대략 80%정도 줄이는 것을 확인 할 수 있다.

Single input change (SIC) test sequence has been investigated in recent years because it is effective to reduce the test power consumption. Deterministic built-in self-test (BIST) can achieve the high fault coverage with relatively short test application time and low test cost. In this paper, seeds selection scheme of SIC sequences based on deterministic ATPG test patterns is proposed for decreasing the test power consumption and test application time with high test fault coverage. Proper selection of SIC seeds is the key aspect to a successful low power deterministic BIST technique. Furthermore, simulated annealing algorithm is used to optimize the numbers of seeds. A simple hardware structure can implement the generation of SIC sequences. Experimental results based on ISCAS'85 benchmark circuits demonstrate that the proposed algorithm can reduce the number of SIC seeds. Test application time and average power can be decreased, and test fault coverage also keep high compared to random SIC (RSIC) test sequences.

Test results judgment method based on BIT faults

Row-pattern-sensitive and column-pattern-sensitive faults in random-access memories (RAMs) are the class of faults in which the contents of a cell are assumed to be sensitive to the contents of the row and column containing the cell. Although the existence of such faults has been argued in the literature, tests to detect such faults have been proposed. The authors formally define a fault model based on the row and column pattern sensitivity. They establish a lower bound on the length of a test sequence required to detect such faults and propose algorithms that generate test sequences of the required length. Although the length of the test sequence is O(N/sup 3/2/), where N is the number of bits in the RAM, the authors believe that the algorithm can be used to test RAMs in built-in self-test environments. >

A new flexible, hierarchical and distributed power-constrained embedded memory built-in self-test (BIST) architecture for complex and heterogeneous systems-on-a-chip (SOCs) is presented. The proposed architecture consists of a shared technology-independent BIST controller, low area and low power memory BIST wrappers and serial interconnect between them for low routing-overhead. Due to its flexibility, in addition to reducing routing complexity and achieving high test concurrency under power constraints, the presented solution can simultaneously support multiple test algorithms for heterogeneous memories, as well as embed custom test algorithms required for new memory faults.

Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

ABSTRACTThis article presents a Bayesian variable selection–based diagnosis approach to simultaneously identify both process mean shift faults and sensor mean shift faults in manufacturing processes. The proposed method directly models the probability of fault occurrence and can easily incorporate prior knowledge on the probability of a fault occurrence. Important concepts are introduced to understand the diagnosability of the proposed method. A guideline on how to select the values of hyper-parameters is given. A conditional maximum likelihood method is proposed as an alternative method to provide robustness to the selection of some key model parameters. Systematic simulation studies are used to provide insights on the relationship between the success of the diagnosis method and related system structure characteristics. A real assembly example is used to demonstrate the effectiveness of the proposed diagnosis method.

Single input change (SIC) sequence for VLSI testing has been researched because of effectiveness to more test fault models and low power consumption testing. It is the high fault coverage in deterministic built-in self-test (BIST) with low test cost and short test application time. The sequential single input change (SSIC) sequence used in deterministic BIST is presented in this paper for decreasing the dynamic power, reducing test application time and increasing fault coverage. The selection of seed vectors is the significant technique in deterministic BIST. The critical features of SSIC sequence are proposed for selecting seed vectors. The SSIC sequence generator is designed. The simulation results using benchmark circuits show that the SSIC sequences can increase fault coverage and decrease application time than random SIC sequences. SSIC sequence also has low dynamic power consumption.