Optimized counting threshold Built-in redundancy analysis for memories

In system on chip (SOC) design, memory occupies a large area, if any defects in the memory that will affect the SOC’s total yield. To avoid this, spare rows and columns are added to the memory. When the fault cells need to be operated, spares rows/columns will be used instead of faulty cells using Built-in self-repair (BISR) logic. Repairing logic includes either row repair/column repair or a combination of both. In this paper, we propose two methods, one is on the memory built-in self-test (BIST) for checking the memory array circuit. In the second method, an optimized BISR is employed to repair the faulty memory cells based upon the Built-in redundancy analysis. In the BIST method, our proposed method injects the faults into memory by using two fault injection techniques called saboteurs and mutants with optimized test pattern logic. After the injection of the faults in the memory cell, the fault memory is repaired with the proposed counting threshold algorithm for the BISR scheme. Simulation and synthesis results are obtained using Mentor Graphics and Xilinx ISE Design Suite. From our obtained results it can be inferred that various performance measures like power, area, and timing details are reduced in the proposed methods when compared with the existing exhaustive methods. And this proves that the performance of the overall process is found to be enhanced. Thereby yield can also be enhanced with minimum time to market.

As advances in memory density and capacity result in an increase in the probability of fault occurrence, many studies on built-in redundancy analysis (BIRA) have been conducted to address this problem. However, conventional BIRAs cannot directly find a final repair solution as soon as test sequences of the built-in self-test (BIST) are over, because they require starting the fault analyses after finishing the test sequences to achieve an optimal repair rate. For this reason, additional analysis time is inevitable, which affects total test costs. In this paper, a dynamic BIRA is proposed for memory repair. It can find a final repair solution directly as soon as test sequences if the BIST are over and achieve an optimal repair rate. The proposed BIRA can restore faults in fault-storing content-addressable memories whenever the spaces in them can be reduced via dynamic fault analysis. Furthermore, the proposed BIRA can be implemented with a reasonable hardware size. This is demonstrated via experiments.

With the growth of memory capacity and density, test cost and yield improvement are becoming more important. In the case of embedded memories for systems-on-a-chip (SOC), built-in redundancy analysis (BIRA) is widely used as a solution to solve quality and yield issues by replacing faulty cells with extra good cells. However, previous BIRA approaches focused mainly on embedded memories rather than commodity memories. Many BIRA approaches require extra hardware overhead to achieve the optimal repair rate, which means that 100% of solution detection is guaranteed for intrinsically repairable dies, or they suffer a loss of repair rate to minimize the hardware overhead. In order to achieve both low area overhead and optimal repair rate, a novel BIRA approach is proposed and it builds a line-based searching tree. The proposed BIRA minimizes the storage capacity requirements to store faulty address information by dropping all unnecessary faulty addresses for inherently repairable die. The proposed BIRA analyzes redundancies quickly and efficiently with optimal repair rate by using a selected fail count comparison algorithm. Experimental results show that the proposed BIRA achieves optimal repair rate, fast analysis speed, and nearly optimal repair solutions with a relatively small area overhead.

The test cost and yield improvement of embedded memories have become very important as memory capacity and density have grown. For embedded memories, built-in redundancy analysis (BIRA) is widely used to improve yield by replacing faulty cells with a 2-D redundancy architecture. However, the most important factor in BIRA is the reduction of hardware overhead while keeping optimal repair rate. Most BIRA approaches require extra hardware overhead in order to store and analyze faults in the memory. These approaches do not utilize spare memories during the redundancy analysis (RA) procedure. However, the proposed BIRA minimizes area overhead by utilizing a part of the spare memory as an address mapping table (AMT). Since storing the faulty memory addresses take most of the extra hardware overhead, the reduced logical addresses produced by the AMT are used to reduce the extra hardware overhead. In addition, the reduced addresses are stored in content-addressable memories (CAMs) and used in the RA procedure. The proposed BIRA can achieve an optimal repair rate by using an exhaustive search RA algorithm. The proposed RA algorithm compares the repair solution candidates with all the fault addresses stored in the proposed CAMs to guarantee an exhaustive search. The experimental results show that the proposed BIRA requires a smaller area overhead than that of the previous state-of-the-art BIRA with an optimal repair rate.

With the development of memory density, the probability of occurring faults in memory also increases. To overcome this problem, many built-in redundancy analysis (BIRA) algorithms have been proposed to repair the faults using redundancy cells in memory. Most of previous algorithms have focused on single memory block with local spare cell architecture. However, many memories in system consist of multiple local memory blocks with various spare cell architectures. Thus, the proposed algorithm is based on not only local spare cell but also various spare cell architectures. The experimental results show that repair rate, and hardware overhead of BIRA with various spare cell architectures in multiple memory blocks. The proposed algorithm is practical solution for multiple memory blocks which have global spare cell and common spare cell.

최근의 시스템 온 칩 (SoC) 설계 기술의 발전에 따라, 수백개의 임베디드 메모리 코어들이 칩의 대부분의 면적을 차지하고 있다. 그러므로 시스템 온 칩의 수율은 임베디드 메모리 코어들의 수율에 따라 결정된다고 볼 수 있다. 최적의 수리 효율을 가지는 built-in self repair (BISR)을 모든 메모리들이 가지고 있게 된다면 면적의 부담이 너무 크다. 본 논문에서는 이와 같은 면적의 부담을 줄이기 위하여 메모리들을 그룹화 한 후에 비트맵 메모리를 공유하여 면적 부담을 크게 줄이는 방법을 제안한다. 제안하는 비트맵 메모리 공유방법은 built-in redundancy analysis (BIRA)의 면적을 크게 줄일 수 있다. 실험결과를 통해서 보면 제안하는 방법이 면적 부담을 대략 80%정도 줄이는 것을 확인 할 수 있다.

A new flexible, hierarchical and distributed power-constrained embedded memory built-in self-test (BIST) architecture for complex and heterogeneous systems-on-a-chip (SOCs) is presented. The proposed architecture consists of a shared technology-independent BIST controller, low area and low power memory BIST wrappers and serial interconnect between them for low routing-overhead. Due to its flexibility, in addition to reducing routing complexity and achieving high test concurrency under power constraints, the presented solution can simultaneously support multiple test algorithms for heterogeneous memories, as well as embed custom test algorithms required for new memory faults.

The rapid growing trend of utilization of re-useable intellectual property (IP) cores for system-on-chip (SOC) design demands an effective, fast and efficient test scheme. This paper presents a unified approach to SOC testing that uses a built-in self-test (BIST) technique based on summations of cores' test output voltages (SOCTOV), which has the advantage of small hardware overhead and fast testing time. The proposed BIST technique is developed in conjunction with our previous proposed BIST technique which is based on weighted sums of selected node voltages (WSSNV) for embedded cores. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique provides a 100% fault diagnosis resolution for locating the faulty core. It is an alternative solution to SOC testing especially when chip area overhead is a critical concern.

Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs. >

Built-In-Self Test (BIST) being one of the techniques which are well known for their ability of providing on-chip testability feature, attracts its usage in today's System-on-Chip (SoC) designs. With the evolution of Network-on-Chip (NoC) communication for complex SoC, the need for fault tolerant systems have increased at a speed. In an attempt to design a good BIST architecture, this paper proposes a Cellular Automata Rule 45 based BIST architecture for star topology NoC. Power, resource utilization and timing reports are generated for the proposed architecture and are compared against the most popular and widely used LFSR based BIST architecture. The results and discussion in this paper put forward the advantages of the proposed architecture when compared to its counterpart.

With the increasing number of embedded memories in the modern system-on-chips (SOCs), the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective technique for memory testing. However, BIST has a negative impact on physical design (e.g., area and routing). Moreover, the grouping and placement of memory BIST controllers also greatly influences the test application time. In this paper, we propose an integer linear programming (ILP) approach to optimize the memory BIST design with both physical design (grouping and placement of memory BIST controllers) and test application time considered. Experimental results consistently show that our approach works well in practice.

For current VLSI designs, there are two kinds of well-accepted digital testing technologies. One is for embedded memories and the other is for the logic. For embedded memories, Built-In-Self-Test (BIST) is used. For the logic, the main solutions are based on scan DFT and automatic test pattern generation (ATPG). However, to reduce the need to use an external tester, and to ease test reuse at the system level, more designs are using BIST to test logic. In the future, with system on chip (SoC) requirements and deep Sub-Micron (DSM) technologies, we believe that BIST and scan-based ATPG will continue to be the main solutions to VLSI testing. However, to be successful, some improvements are needed. The author discusses future trends in three categories: test quality, test application cost and test development effort.

A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (/spl les/2/sup 30/) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%.

The utilization of re-useable Intellectual Property (IP) cores for System-on-Chip (SoC) design can shorten the time-to-market and thus reduce the design cost but on the other hand, the challenge of testing such embedded IP cores is initiated. This paper presents a Built-In Self-Test (BIST) technique based on the weighted sum of selected node voltages (WSSNV) for the effective testing of these embedded cores. The proposed BIST technique can greatly reduced the number of testing I/O pins and thus reduce the size and simplify the design of test architecture for SoC. Besides, testing time and procedure are reduced and simplified respectively since only one testing output is needed to be observed.

Mixed signal circuits typically require more complex specification based testing as compared to digital circuits, which can be completely tested with structural or simple functional tests. Due to the analog nature of some of the internal nodes and external signals in mixed signal circuits, qualitative functional tests may be required to assure circuit performance at all operating points. Mixed signal blocks such as Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) act as interfaces between the digital processing modules of the System on a Chip (SoC) and interfacing analog domains. These converters are increasingly common on SoCs due to ever-increasing presence of real world analog signals that use the processing capabilities of the digital blocks. High volume production testing of these mixed-signal components is inefficient due to test complications, resulting in the use of high-performance Automatic Test Equipment (ATE). While various Built-in Self Test (BiST) schemes are proposed to provide the analog test stimulus, the conventional histogram analysis method is still in use for the majority of ADC testing applications. We review a proposal for ADC output test involving a functional pattern, effectively resulting in a real-time-code-analysis. Memory and processing constraints for the ATE are reduced as this vector based method is not ATE memory intensive while providing an output quality measure identical to the conventional histogram method.