Cellular Automata based Built-In-Self Test implementation for Star Topology NoC

In this research, a BIST (built in self test) architecture for testing crosstalk effects in highly dense Through Silicon Via (TSV) placed in structured array form, in 3DICs (Three Dimensional integrated circuits), designed and simulated using the Xilinx ISE tool and the VHDL language. A novel methodology is proposed, and simulated, to observe the test responses of the victim TSVs in the chosen group simultaneously. Boundary-scan cell structures are modified, created for the purpose of operating in different modes such as shift, update and capture in either conventional serial shift mode as well as in proposed parallel broadcasting mode. Output Response Analyzers (ORA), or signature analyzers that have been simulation-verified. In this study, we suggested a novel encoder-based signature generator to locate faulty TSVs in the parallel-observed TSVs. This paper discusses the whole BIST architecture, the BIST controller built on an algorithmic state machine, the design of TPG (Test Pattern Generator), and the faulty TSV signature generator. Comparing the BIST architecture, to serial shift based interconnect tests done by IEEE 1149.1 (JTAG) such as EXTEST and IEEE 1838 standards, the test’s time complexity of BIST is relatively very low. The entire TSV array test is completed in just 32 clock cycles. The design is adaptable and can be used to broadcast test patterns to a group or to transmit test patterns serially using IEEE 1838 or 1149.1.

We present a scalable BIST (Built-In Self Test) architecture that provides a tunable trade-off between on-chip area demand and test execution time for delay fault testing. So, the architecture can meet test execution time requirements, area requirements, or any target in between. Experiments show the scalability of our approach, e.g., that considerably shorter test execution time can be achieved by storing only a few additional input vectors of the BIST architecture. The gain of test execution time possible with the proposed method ranges from a factor of 2 up to a factor of more than 800000.

A new flexible, hierarchical and distributed power-constrained embedded memory built-in self-test (BIST) architecture for complex and heterogeneous systems-on-a-chip (SOCs) is presented. The proposed architecture consists of a shared technology-independent BIST controller, low area and low power memory BIST wrappers and serial interconnect between them for low routing-overhead. Due to its flexibility, in addition to reducing routing complexity and achieving high test concurrency under power constraints, the presented solution can simultaneously support multiple test algorithms for heterogeneous memories, as well as embed custom test algorithms required for new memory faults.

This paper introduces new design and synthesis techniques that reduce the area and performance overhead of built-in self-test (BIST) architectures such as circular BIST and parallel BIST. Our goal is to arrange the system bistables into scan paths such that some of the BIST and scan logic is shared with the functional logic. Logic sharing is possible when scan dependence is introduced in the design. Other BIST design techniques attempt to avoid scan dependence because it can reduce the fault coverage of embedded, multiple input signature registers (MISRs). We show that introducing certain types of scan dependence in embedded MISRs can result in reduced overhead and improved fault coverage. We present our results for benchmark circuits that have been synthesized to take advantage of scan dependence in a circular BIST architecture.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SOCs are application-specific standard products (ASSPs) with limited programmability We describe why TV SOCs must become more flexible, and why companion chips together with networks on chips (NOC) are a crucial enabling technology In particular, networks that span multiple chips will become important in the near future. We demonstrate our ideas by extending a commercially-available SOC for picture improvement in high-end TVs with the /Ethereal NOC. Our first unoptimised results indicate that replacing the original interconnect (consisting of dedicated links and multiplexers for bypasses) by programmable NOC increases the SOC area by 4% and its power dissipation by 12%. The new, flexible SOC allows new tasks to be spliced in at any point in the task graph. Both analytical performance verification and system simulations at RTL VHDL show that the extended SOC meets its functional requirements. Using the /Ethereal design flow the extended architecture was designed, implemented, and verified in 12 person months. To the best of our knowledge, this is the first application of a NOC to a commercial SOC. The quantitative results indicate that even retrofitting a NOC to an existing architecture is beneficial at acceptable cost

The technique of Test Sequence Generation (TSG) plays a key role in Built-In Self-Test (BIST) architecture implementation. Major problem with any test sequence generator is to produce long, unpredictable key sequences which can be applied to Circuit Under Test (CUT) in order to detect the faults efficiently. Digital Systems/Circuits are tested by inducing appropriate stimuli and checking the responses generated. Generation of such stimuli together with calculation of their anticipated responses is called Test Sequence Generation or Test Pattern Generation. Due to certain limitations of Automatic Test Equipment (ATE), there exist methods where the main functions of the external tester have been moved onto the chip, Such DFT practice is generally known as BIST. With the progression of test technology, various techniques have been developed for IC testing. This paper presents three techniques: Cellular Automata (CA), Linear Feedback Shift Register (LFSR), and Single Bit Change Sequence Generator (SBCSG), used for test pattern generation and test response analysis in a typical BIST circuit. All the three TPGs are analyzed with respect to the parameters like Power, Time and Area to demonstrate their shortfalls and suitability for intended application.

This paper presents a low-cost low-power self-test design and verification of on-chip analog-to-digital converter (ADC) for System-on-a-Chip (SoC) applications. A methodology for performing mixed-mode built-in self-test (BIST) simulation was performed along with the BIST architecture. The architecture presented allows for generation of analog test signals of frequency up to 600 MHz, using a 4-b 2.5 Gsamples/s current steering digital-to-analog converter (DAC). Both integral nonlinearity (INL) and differential nonlinearity (DNL ) errors of test signals were obtained about 0.5 LSB by the sine wave histogram testing. The measured power dissipation for generated test signals of 600 MHz at the power supply of 1.2 V is about 5.32 mW. The current steering DAC achieves 22.3 dB of spur free dynamic range (SFDR) for 600 MHz signals.

The rapid growing trend of utilization of re-useable intellectual property (IP) cores for system-on-chip (SOC) design demands an effective, fast and efficient test scheme. This paper presents a unified approach to SOC testing that uses a built-in self-test (BIST) technique based on summations of cores' test output voltages (SOCTOV), which has the advantage of small hardware overhead and fast testing time. The proposed BIST technique is developed in conjunction with our previous proposed BIST technique which is based on weighted sums of selected node voltages (WSSNV) for embedded cores. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique provides a 100% fault diagnosis resolution for locating the faulty core. It is an alternative solution to SOC testing especially when chip area overhead is a critical concern.

Network on Chip (NoC) is an emerging interconnect solution with reliable and scalable features over the System on Chip (SoC) and helps to overcome the drawbacks of bus-based interconnection in SoC. The multiple cores or other networks have a boundary which is limited to communicate with devices, which are directly connected to it. To communicate with these multiple cores outside the boundary, the NOC requires the gateway functionality. In this manuscript, a cost-effective Network Gateway (NG) model is designed, and also the interconnection of a network gateway with multiple cores are connected to the NoC based system is prototyped on Artix-7 FPGA. The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch is connected with multiple cores which are controlled by switch controller. The NG with the Router and different sizes of NoC based system is designed using congestion-free adaptive-XY routing. The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR). The proposed Network gateway achieves low latency and high throughput in NoC based systems for different PIR.

Background/objectives: The major contribution in very large scale integrated circuits is given by System on Chip (SoC) technology. Many fuzzy logics are been implemented on SoC’s and are effectively supported by them. In time the Networks came into existence and interconnection of networks became very necessary so Network on Chips (NoC) was implemented and many topologies were also suggested. The main aim of this paper is to find an effective on-chip topology for network on chips. Methods/Statistical Analysis: Topologies related to this network on chips gives different routing algorithms which defines the direction of the route. Different algorithms were proposed for different topologies defining the direction, traffic rate at which the packet is entering, latency, and throughput. These were considered as the main trade off’s for Network on Chip. Findings: in this paper discussion on 4 topologies was done by taking few main properties into account and implementation of the topologies were done in software. It was found that latency and throughput plays a major role in the topology and along with these 2 the packet rate and flit rate also play a key role. The values of all trade-offs for every topology were taken and graphs were plotted showing the variation between the topologies. The efficiency of each topology can be observed in respective graph. Application/Improvements: Network on chips is used in routers and these can be further improved in to wireless connections.

Network on-Chip (NoC) is a novel technology which is used to make the interconnections between the components available in the System on Chip (SoC) design. This technology of NoC is defined and used in two varied forms as buffered and bufferless NoC. Bufferless NoC, a predominant type of network on chip, is used to reduce the cost efficiently by removing input buffers of the router. However, it is evident that this performance gets jammed at high loads because of the increase in the network contentions and deflection of packets in huge amount. To reduce the amount of deflection and to buttress the flow, Clumsy Flow Control (CFC) is used in the bufferless NoC. In this paper, a novel proposal has been propounded into the pipelining mechanism keeping in mind the flawless flow control needed for the bufferless NoC to decrease the impact of deflection routing and to increase the throughput with high injection rate. Employing the pipelining technique into the existing flow control increases the frequency which in turn, is responsible for high throughput. Implementation of the aforementioned pipelining mechanism is done in two stages in the bufferless NoC which helps to increase the throughput as well as the injection rate. Finally, the application with its pipelined implementation, as proposed, will be mapped onto the NoC architecture by using the CFC.

A VHDL based Fault simulation procedure for test bench and test hardware evaluation has been developed. This work is aimed to utilize features of VHDL for more efficient fault simulation. Information about fault detection can be obtained in this environment using fault simulation method and guidelines presented in this report. This environment consists of automated steps, which will lead to fault simulation. Information such as fault coverage, efficiency of test patterns and capability of test hardware to detect faults, can be extracted. Using this environment, one can evaluate test benches and order test vectors or configure BIST (Built-In Self Test) architectures.

We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths. Test patterns are generated on-chip by carefully reseeding the TRC. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits. Instead of being stored on-chip, the seed patterns can also be scanned in using a low-cost, slower tester. The seeds can be viewed as an encoded version of the test set that is stored in tester memory. This requires almost 10X less memory than compacted test sets obtained from ATPG programs. This allows us to effectively combine high-quality BIST with external testing using slow testers. As the cost of high-speed testers increases, methodologies that facilitate testing using slow testers become especially important. The proposed approach is a step in that direction.

Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip (SoC) which supports high degree of scalability and reusability. One of the most important issues in an NoC design is how to map an application on NoC-based architecture in order to satisfy the performance and cost requirements. In this paper a novel procedure is introduced to find an optimal application-specific NoC using Particle Swarm Optimization (PSO) and a linear function which considers communication cost, robustness index and contention factor. Communication cost is a common metric in evaluation of different mapping algorithms which have direct impact on power consumption and performance of the mapped NoC. Robustness index is used as a criterion for estimating fault-tolerant properties of NoCs and contention factor highly affects the latency, throughput and communication energy consumption. The experimental results on two real core graphs VOPD and MPEG-4 reveal the power of proposed procedure to explore design space and how effective designer can customize and prioritize the impact of metrics.

The increasing complexity of System on a Chip (SOC) using Network on a Chip (NoC) results in significant increases in traditional verification times. Formal methods fully prove design properties, without deadline vs. coverage compromises, hence tremendously reducing time to market. In this work we use the CONNECT NOC to illustrate our new white box formal verification methodology. We develop constraints and assertions for properties verification. Our methodology is faster than the current methods; it also uncovered key gaps in current practices. In addition, our assertion checkers can be reused both in simulation and as monitors on silicon.