Model Checking Formal Verification Methodology for Virtual Channel NoCs

Use of Network on Chips (NoCs) as a flexible communication infrastructure is becoming a norm for designing advanced System on Chips (SoCs). However, their implementation complexity is enormous and use of industry proven functional verification methodologies start showing their limitations. Recent research activities have demonstrated that formal verification is capable of addressing most of the bottlenecks faced by functional verification techniques. In this context, this paper presents a survey on recent advances in the field of "Formally verifying a Network on Chip (NoC)". An overview of NoC design challenges is presented along with their formal verification methodologies. The paper concludes by highlighting that going forward, a Unified Formal Verification Methodology (UFVM) must be driven to ensure that the benefits of formal verification are reaped.

Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SOCs are application-specific standard products (ASSPs) with limited programmability We describe why TV SOCs must become more flexible, and why companion chips together with networks on chips (NOC) are a crucial enabling technology In particular, networks that span multiple chips will become important in the near future. We demonstrate our ideas by extending a commercially-available SOC for picture improvement in high-end TVs with the /Ethereal NOC. Our first unoptimised results indicate that replacing the original interconnect (consisting of dedicated links and multiplexers for bypasses) by programmable NOC increases the SOC area by 4% and its power dissipation by 12%. The new, flexible SOC allows new tasks to be spliced in at any point in the task graph. Both analytical performance verification and system simulations at RTL VHDL show that the extended SOC meets its functional requirements. Using the /Ethereal design flow the extended architecture was designed, implemented, and verified in 12 person months. To the best of our knowledge, this is the first application of a NOC to a commercial SOC. The quantitative results indicate that even retrofitting a NOC to an existing architecture is beneficial at acceptable cost

Network on Chip (NoC) is an emerging interconnect solution with reliable and scalable features over the System on Chip (SoC) and helps to overcome the drawbacks of bus-based interconnection in SoC. The multiple cores or other networks have a boundary which is limited to communicate with devices, which are directly connected to it. To communicate with these multiple cores outside the boundary, the NOC requires the gateway functionality. In this manuscript, a cost-effective Network Gateway (NG) model is designed, and also the interconnection of a network gateway with multiple cores are connected to the NoC based system is prototyped on Artix-7 FPGA. The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch is connected with multiple cores which are controlled by switch controller. The NG with the Router and different sizes of NoC based system is designed using congestion-free adaptive-XY routing. The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR). The proposed Network gateway achieves low latency and high throughput in NoC based systems for different PIR.

Background/objectives: The major contribution in very large scale integrated circuits is given by System on Chip (SoC) technology. Many fuzzy logics are been implemented on SoC’s and are effectively supported by them. In time the Networks came into existence and interconnection of networks became very necessary so Network on Chips (NoC) was implemented and many topologies were also suggested. The main aim of this paper is to find an effective on-chip topology for network on chips. Methods/Statistical Analysis: Topologies related to this network on chips gives different routing algorithms which defines the direction of the route. Different algorithms were proposed for different topologies defining the direction, traffic rate at which the packet is entering, latency, and throughput. These were considered as the main trade off’s for Network on Chip. Findings: in this paper discussion on 4 topologies was done by taking few main properties into account and implementation of the topologies were done in software. It was found that latency and throughput plays a major role in the topology and along with these 2 the packet rate and flit rate also play a key role. The values of all trade-offs for every topology were taken and graphs were plotted showing the variation between the topologies. The efficiency of each topology can be observed in respective graph. Application/Improvements: Network on chips is used in routers and these can be further improved in to wireless connections.

Network on-Chip (NoC) is a novel technology which is used to make the interconnections between the components available in the System on Chip (SoC) design. This technology of NoC is defined and used in two varied forms as buffered and bufferless NoC. Bufferless NoC, a predominant type of network on chip, is used to reduce the cost efficiently by removing input buffers of the router. However, it is evident that this performance gets jammed at high loads because of the increase in the network contentions and deflection of packets in huge amount. To reduce the amount of deflection and to buttress the flow, Clumsy Flow Control (CFC) is used in the bufferless NoC. In this paper, a novel proposal has been propounded into the pipelining mechanism keeping in mind the flawless flow control needed for the bufferless NoC to decrease the impact of deflection routing and to increase the throughput with high injection rate. Employing the pipelining technique into the existing flow control increases the frequency which in turn, is responsible for high throughput. Implementation of the aforementioned pipelining mechanism is done in two stages in the bufferless NoC which helps to increase the throughput as well as the injection rate. Finally, the application with its pipelined implementation, as proposed, will be mapped onto the NoC architecture by using the CFC.

Network-on-Chip (NoC) is a popular communication and interconnection structure for multi or many-core system-on-chip (SoC). It mainly consists of routers, network interfaces and communication links. It typically utilizes virtual channels (VCs) to improve wormhole routing among the SoC cores by enabling multiple packet flits to share NoC communication links. DAMQ (Dynamically Allocation Multi Queues) based VC organization has higher buffer utilization but it also has a few problems. We present a novel NoC router architecture that provides solutions to these problems. It utilizes dynamic VC based buffering and index based arbitration methodologies. Arbitration is a critical operation employed in NoC routers that may results in lower speed, weak fairness, and difficulties in pipelining. Our arbitration techniques used in the presented router architecture overcome these problems. We have simulated and implemented our 2D-mesh NoC router using System-Verilog. The experimental results confirm the efficiency of our proposed NoC router in terms of superior router power and ASIC area as well as its operating speed. Performance metrics for different NoC configurations are determined and evaluated for a variety of traffic patterns.

Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip (SoC) which supports high degree of scalability and reusability. One of the most important issues in an NoC design is how to map an application on NoC-based architecture in order to satisfy the performance and cost requirements. In this paper a novel procedure is introduced to find an optimal application-specific NoC using Particle Swarm Optimization (PSO) and a linear function which considers communication cost, robustness index and contention factor. Communication cost is a common metric in evaluation of different mapping algorithms which have direct impact on power consumption and performance of the mapped NoC. Robustness index is used as a criterion for estimating fault-tolerant properties of NoCs and contention factor highly affects the latency, throughput and communication energy consumption. The experimental results on two real core graphs VOPD and MPEG-4 reveal the power of proposed procedure to explore design space and how effective designer can customize and prioritize the impact of metrics.

The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these methods have to address are the generation and evaluation of network traffic. Traffic generation allows injecting packets in the network according to application constraint specifications such as transmission rate and end-to-end latency. Performance evaluation helps in computing latency and throughput at network channels/interfaces, as well as to identify congestion and hot-spots. This paper reviews related works in traffic generation and performance evaluation for mesh topology NoCs, and proposes general methods for both aspects. Three parameters are used here to define traffic generation: packet spatial distribution, packet injection rate and packet size. Two types of methods to evaluate performance in NoCs are discussed: (i) external evaluation, a common strategy found in related works, where the network is considered as a black box and traffic results are obtained only from the external network interfaces; (ii) internal evaluation, where performance is computed in each network channel. The paper presents the result of experiments conducted in an 8times8 mesh network, varying the routing algorithms and the number of virtual channels. The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios

Over the years, system on chip (SoC) designs have evolved extensively sophisticated in order to fulfil the need of increasing complexity of running applications driven by the advancement of VLSI technology. The next generation multiprocessor system on chip (MPSoC) integrates hundreds of processing elements on a single chip, expected to achieve high performance, low latency, and low-power consumption. Tiled chip multicore processors (TCMP) with network on chip (NoC) have become a foundation for the computation critical embedded and real-time systems. Faster time-to-market restraint and business competition compelled manufacturers to look for the prospects of manufacturing SoCs integrated with various third party intellectual property (3PIP). Usage of 3PIP gave rise to exploit the underlying interconnect while adding some unwanted malicious circuit known as hardware trojan (HT), making NoC vulnerable to get attacked. A tiniest manipulation of any communication attribute by HT can degrade the overall behaviour of the system significantly while impacting NoC performance metrics. In this paper, we present one of such study considering HT malign behaviour of manipulating the output port of each incoming flit from specific ports once genuine route computation takes place and re-directs all to one port causing disruption in tile communication.The proposed HT is intermittent in nature and activates for few cycles. We study the behaviour of proposed confluence attack and analyze its impact over network level. The empirical evaluation exhibits the misbehaviour of the packet communication in terms of wrong usage of VCs and extra hop distance overhead. To validate the proposed work, various performance metrics like buffer utilization, virtual channel utilization, number of flits processed, link utilization, and the like are analyzed. We also show that such HTs are difficult to detect due to marginal increase at malicious port traffic leaving no trace of malicious conduct.

The Network on chip (NOC) architectures provide routing mechanism for various IP blocks in a system on chip (SOC). The existing schemes are based on the techniques are used in networking protocols similar to the conventional Ethernet communication. Such schemes suffer from data overheads and high complexity protocols. A technique based on Direct Sequence Spread Spectrum (DSSS) is proposed with scalable architecture for meeting NOC requirements. High level architecture for data transmission and addressing scheme is designed and simulated in VHDL. The complete scheme is prototyped on Spartan 3E FPGA. The results demonstrate the suitability of the proposed scheme for medium scale SOC applications.

Bio-inspired solutions are used to solve the real-world problems as they are able to resolve the complex issues. Already existing bio-inspired solutions are reviewed in this chapter which solved the complex engineering problems. Moreover, this chapter also discusses the implementation of biological brain mechanism in Network on Chip to address the fault-tolerant issues. Network on Chip (NoC) is a communication framework for System on Chip (SoC). Due to routers and interconnect failure, NoC suffers from faults. Therefore, bio-inspired solutions help us to recover from these faults. The techniques from the biological brain were implemented in NoC as the brain is fault tolerant and highly adaptive. Results showed that bio-inspired techniques are performing well compared to the traditional fault-tolerant algorithms.

In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System on-Chip (SoC) application. We present several design choices and focus on the power optimization of the NoC while achieving the required performance. Our design steps include module mapping and allocation of customized capacities to links. Unlike previous studies, in which point-to-point, per-flow timing constraints were used, we demonstrate the importance of using the application end-to-end traversal latency requirements during the optimization process. In order to evaluate the different alternatives, we report the synthesis results of a design that meets the actual throughput and timing requirements of the commercial SoC. According to our findings, the proposed technique offers up to 40% savings in the total router area and a reduction of up to 49% in the inter-router wiring area.

QNoC: QoS architecture and design process for network on chip

Network on chip (NoC) is a new design paradigm for building scalable core-based systems on chip (SoC). Multithreading is a technique for hiding long latencies of memory accesses, through the overlapped execution of several threads. In this paper, we make a case for using multi-threaded processors (MTP) as resources in NoC and describe a methodology for off-line mapping and scheduling of concurrent applications to NoC with MTPs. The experimental results show a speedup of 15% on average for a 2/spl times/2 NoC when using two MTPs with 3-thread contexts instead of two general processors (GP).

Systems on chip (SoC) are becoming increasingly complex, with a large number of applications integrated on the same chip. Such a system often supports a large number of use-cases and is dynamically reconfigured when platform conditions or user requirements change. Networks on chip (NoC) offer the designer unsurpassed runtime flexibility. This flexibility stems from the programmability of the individual routers and network interfaces. When a change in use-case occurs, the application task graph and the network connections change. To mitigate the complexity in programming the many registers controlling the NoC, an abstraction in the form of a configuration library is needed. In addition, such a library must leave the modified system in a consistent state, from which normal operation can continue. In this paper we present the facilities for controlling change in a reconfigurable NoC. We show the architectural additions and the many trade-offs in the design of a run-time library for NoC reconfiguration. We qualitatively and quantitatively evaluate the performance, memory requirements, predictability and reusability of the different implementations