Dynamic current modeling at the instruction level

There is a continuous drive for methodologies and approaches of low power design. This is mainly driven by the surge in portable computing. On the other hand, the design of low power systems for different portable applications is not a simple task. This is because of the number of constraints that influence the power consumption of a device. In addition to issues of performance and functionality, there is a need to satisfy strict test coverage constraints. The author investigate the impact of DSP architectural realisation, multiplier type, and the choice of number representation on the overall power consumption of DSP devices. Work in the literature so far has concentrated on the effect of these on a part or a section of a DSP system. Furthermore the effect of DfT circuits on the overall performance is studied. A hearing aid device is considered as an example of a system with strict power/area constraints. It is shown that the choice of multiplier architecture and number representation should be carefully considered when specific DSP architectural choices are made. The results are demonstrated with a number of specially designed DSP architectures for the implementation of FIR filtering algorithms on hearing aid devices.

The modern era of embedded system design is geared towards design of low-power systems. One way to reduce power in an ASIC implementation is to reduce the bit-width precision of its computation units. This paper describes algorithms to optimize the bit-widths of fixed point variables for low power in a SystemC design environment. We propose an algorithm for optimal bit width precision for two variables and a greedy heuristic which works for any number of variables. The algorithms are used in the automation of converting floating point SystemC programs into ASIC synthesizable SystemC programs. Expected inputs are profiled to estimate errors in the finite precision conversions. Experimental results on the trade-offs between quantization error, power consumption and hardware resources used are reported on a set of four SystemC benchmarks that are mapped onto 0.18 micron ASIC cell library from Artisan Components. We demonstrate that it is possible to reduce the power consumption by 50% on average by allowing round-off errors to increase from 0.5% to 1%. 1

This paper proposes a study on how pipelining technology can be used in Vedic multipliers, employing Urdhava Tiryakbhyam sutra, to increase the speed and reduce the power consumption of a system. Pipelining is one of the methods used in the design of low-power systems. Vedic multipliers use an ancient style of multiplying numbers which allows for easier and faster calculations, compared to the regular mathematical method. The concept of pipelining, when used in these multipliers, leads to a system which computes calculations faster using lesser hardware. The study includes the direct use of pipelining in 2 × 2 bit, 4 × 4 bit, 8 × 8 bit and 16 × 16 bit Vedic multipliers. The pipelining is then further incorporated at different levels to create 8 × 8 bit and 16 × 16 bit multipliers. The algorithm of the system is implemented on Spartan 3E field-programmable gate array (FPGA). The designed system uses lesser power and has lower delay compared to the existing systems.

The conventional method for identifying the transfer function of an unknown linear system consists of a least squares fit of its input to its output. It is equivalent to identifying the frequency response of the system by calculating the empirical cross-spectrum between the system's input and output, divided by the empirical auto-spectrum of the input process. However, if the additive noise at the system's output is correlated with the input process, e.g., in case of environmental noise that affects both system's input and output, the method may suffer from a severe bias effect. We present a modification of the cross-spectral method that exploits nonstationary features in the data in order to circumvent bias effects caused by correlated stationary noise. The proposed method is particularly attractive to problems of multichannel signal enhancement and noise cancellation, when the desired signal is nonstationary in nature, e.g., speech or image.

Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital very-large-scale-integration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand high-speed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of high-end products to keep power under control, due to the increased costs of packaging and cooling this type of device. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of low-power VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature.

Approximate computing is a promising approach in the design of low-power digital systems. There are two main approaches in approximate computing: the first relies on lowering the supply voltage level on specific computational blocks, while the second relies on completely truncating specific computational blocks. The second option is more aggressive; however, it is deterministic and leads to better energy savings. This paper, in accordance with the second option, presents a set of 8-bit combinational digital multipliers that provide an approximate product while reducing energy consumption by up to 57% while maintaining excellent results, as demonstrated by several image-processing applications.

Energy-efficient compact alternatives to fully digital computing strategies could be achieved by implementations of artificial neural networks (ANNs) that borrow analog techniques. In-memory computing based on crossbar device architectures with memristive materials systems that execute, in an analog way, multiply-and-accumulate operations prevalent in ANN is a notable example. Ferroelectric (FE) materials are promising candidates for achieving ANN thanks to their excellent down-scalability, improved electrical control, and high energy efficiency. However, it remains challenging to develop a crossbar device architecture using FE materials. The difficulty stems from decreasing the leakage current of FE hardware and, simultaneously, reducing the film thickness for achieving compact systems. Here, we have performed density-functional-theory calculations to investigate the electronic, energy-based, and structural signatures of wurtzite FE material Al0.75Sc0.25N with a nitrogen vacancy (VN) in different charge states. We find that VN can introduce two defect states, viz., the singlet state above the valence band maximum (VBM) and a triplet state below the conduction band minimum in wurtzite AlScN models. The calculations reveal that the group of transition levels E3+/2+/E2+/1+ with small formation energies occur at ∼0.78/1.03 eV above the VBM in the wurtzite AlScN with a relaxed configuration, which may shift by a large degree to lower energy levels if atoms surrounding the defect are not fully relaxed. Theoretical studies elucidate the vacancy-enhanced increase in the leakage current utilizing large AlScN supercells. These findings render atomistic insights that can provide a path forward for the design of next-generation portable low-power electronic systems.

This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120µm2) single p-well (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. The results from a 140kb programmable dynamic SRAM characterization test module provide both information about location and cause of failures as well as power and performance by mimicking system operating conditions over a wide supply voltage range. A 410mV minimum operating voltage and less than 310mV data retention voltage with a leakage current close to 100fA/bitcell are measured. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.

The increasing demands for multimedia and wireless communication applications have had much impact on design of high-speed and low-power modern DSP systems. Orthogonal IIR digital filters can achieve a sharp transition band and have good finite word-length behavior and are used in many modern DSP applications such as mobile communications. However, Cordic-based fine-grain pipelined true orthogonal IIR digital filters have not been developed so far. A state-space-based novel algorithm for designing fine-grain pipelined true orthogonal IIR digital filters is proposed using the matrix lookahead technique. The algorithm only involves applying orthogonal transformations that are known to be numerically very reliable, and therefore is ideal for VLSI implementations. The proposed filter architecture can be operated at arbitrarily high sample rates and achieves linear increase in hardware complexity with respect to the filter order and pipelining level. It consists of only Givens rotations which can be mapped onto Cordic arithmetic-based processors. Finally, an intermediate frequency filter for the USA mobile telephone system is designed using the proposed orthogonal filter synthesis algorithm.

This paper reviews the applications of artificial intelligence (AI) in the design optimization of wind power systems, mainly including (1) wind farm layout optimization; (2) wind turbine design optimization; and (3) wind farm electrical system design optimization. Firstly, this paper introduces the general considerations in the optimal design of wind power systems and the AI methods commonly used for the optimal design of wind power systems. Then the applications of AI in the optimal design of wind farms are reviewed in detail. Finally, further research directions of using AI methods in the optimal design of wind power systems are recommended.

Satellites are indispensable for broadcast, weather forecast, navigation, and many other applications, but their design entails a number of stringent requirements, such as limited space and weight, impossible/costly online repairs, severe radiation, and a wide range of temperature they have to withstand. These requirements can only be met by an effective, robust co-design of physical and computing (control) parts of each satellite, making them prototypical cyber-physical systems (CPSes). Of the various CPS issues related to satellites, this paper focuses on offline design and online management of satellite power systems. Specifically, we analyze and model unique characteristics of power supply and demand of a satellite, which are dictated by the periodicity of power generation from solar panels and the nonlinear behavior of rechargeable battery cells. Based on the understanding of these characteristics, we first propose how to find the best configuration (e.g., the number, the arrangement, and the type) of solar panels and battery cells at design time, such that all tasks can be executed without power shortage throughout the satellite's mission lifetime. Second, we propose how to manage power online so as to execute the highest QoS versions of tasks (thus yielding the most power-effective performance) without compromising the power-sufficiency guarantee under a given configuration. As a case study, we study cubic-shaped nanosatellites, which have been launched multiple times since 2004. We borrow their architecture, configuration and parameters, and demonstrate the effectiveness of our design and management of satellite power systems.

Multilayer perceptron and radial basis function neural networks have been traditionally used for plant identification in power systems applications of neural networks. While being efficient in tracking the plant dynamics in a relatively small system, their performance degrades as the dimensions of the plant to be identified are increased, for example in supervisory level identification of a multimachine power system for wide area control purposes. Recurrent neural networks can deal with such a problem by modeling the system as a set of differential equations and with less order of complexity. Such a recurrent neural network identifier is designed and implemented for supervisory level identification of a multimachine power system with a FACTS device. Simulation results are provided to show that the neuroidentifier can track the system dynamics with sufficient accuracy

Backpropagation algorithm is the most commonly used algorithm for training artificial neural networks. While being a straightforward procedure, it suffers from extensive computations, relatively slow convergence speed and possible divergence for certain conditions. The efficiency of this method as the training algorithm of a radial basis function neural network (RBFN) is compared with that of particle swarm optimization, for neural network based identification of a small power system with a static compensator. The comparison of the two methods is based on the convergence speed and robustness of each method.

Identification and control of large-scale power systems are two major problems for industrial engineering applications. In this paper, we develop a state-space model for an AC turbogenerator in noisy environment, using output error model identification approach. A robust variable structure controller which count for uncertainty in the input matrix (B-matrix) is implemented using the developed state-space model. The controller was designed off-line based on a set of expected system uncertain modes and switched online when failure was detected.

Summary form only given. In this paper, the authors use the numerical algorithm for subspace state space system identification (N4SID) to extract dynamic parameters from phasor measurements collected on the western North American Power Grid. The data were obtained during tests on June 7, 2000, and they represent wide area response to several kinds of probing signals including low-level pseudo-random noise (LLPRN) and single-mode square wave (SMSW) injected at the Celilo terminal of the Pacific HVDC Intertie (PDCI). An identified model is validated using a cross validation method. Also, the obtained electromechanical modes are compared with the results from Prony analysis of a ringdown and with signal analysis of ambient data measured under similar operating conditions. The consistent results show that methods in this class can be highly effective even when the probing signal is small.