Smart Bit-width Allocation for Low Power Optimization in a SystemC based ASIC Design Environment

There is a continuous drive for methodologies and approaches of low power design. This is mainly driven by the surge in portable computing. On the other hand, the design of low power systems for different portable applications is not a simple task. This is because of the number of constraints that influence the power consumption of a device. In addition to issues of performance and functionality, there is a need to satisfy strict test coverage constraints. The author investigate the impact of DSP architectural realisation, multiplier type, and the choice of number representation on the overall power consumption of DSP devices. Work in the literature so far has concentrated on the effect of these on a part or a section of a DSP system. Furthermore the effect of DfT circuits on the overall performance is studied. A hearing aid device is considered as an example of a system with strict power/area constraints. It is shown that the choice of multiplier architecture and number representation should be carefully considered when specific DSP architectural choices are made. The results are demonstrated with a number of specially designed DSP architectures for the implementation of FIR filtering algorithms on hearing aid devices.

Estimation of processor current consumption is important for the design of low power systems. This paper proposes a novel method for estimating the dynamic current consumption of a processor. The method models dynamic current as the output of a linear system excited by a signal comprised of the total current due to each instruction. System identification is performed by cross-correlation of a pseudo-random stimulus with the measured current. The method was applied to the Texas Instruments TMS320VC5510 DSP and was found to provide an average correlation of 93% between estimated and measured dynamic current across a range of benchmarks.

This paper proposes a study on how pipelining technology can be used in Vedic multipliers, employing Urdhava Tiryakbhyam sutra, to increase the speed and reduce the power consumption of a system. Pipelining is one of the methods used in the design of low-power systems. Vedic multipliers use an ancient style of multiplying numbers which allows for easier and faster calculations, compared to the regular mathematical method. The concept of pipelining, when used in these multipliers, leads to a system which computes calculations faster using lesser hardware. The study includes the direct use of pipelining in 2 × 2 bit, 4 × 4 bit, 8 × 8 bit and 16 × 16 bit Vedic multipliers. The pipelining is then further incorporated at different levels to create 8 × 8 bit and 16 × 16 bit multipliers. The algorithm of the system is implemented on Spartan 3E field-programmable gate array (FPGA). The designed system uses lesser power and has lower delay compared to the existing systems.

State-of-the-art speaker verification systems are built around the likelihood ratio test, using Gaussian mixture models (GMM) for likelihood functions, a universal background model (UBM) for alternative speaker representation, and a form of Bayesian adaptation to derive speaker models from the UBM. This work tackles optimal quantizer design of the speech cepstral features (MFCCs) for such systems. The problem is posed as the minimization of loss of log-likelihood ratio between the quantized and unquantized speech features. First we show that the conventional mean squared error (MSE) quantizer for the top-scoring UBM Gaussian is optimal under practical assumptions. Then we derive the optimal bit allocation strategy across the dimensions of the feature vectors. Finally we demonstrate the validity of the approach against various quantization and bit allocation schemes by running experiments on the appropriately modified IBM speaker verification system. Experimental results on the HUB4 corpora show negligible impact on verification performance for bit rates as low as less than 1 bit per dimension on average in contrast to 32 bits per dimension in the original system

In the multiview video plus depth (MVD) coding format, both texture and depth views are jointly compressed to represent the 3-D video content. The MVD format enables synthesis of virtual views through depth-image-based rendering; hence, distortion in the texture and depth views affects the quality of the synthesized virtual views. Bit allocation between texture and depth views has been studied with some promising results. However, to the best of our knowledge, most of the existing bit-allocation methods attempt to allocate a fixed amount of total bit rate between texture and depth views; that is, to select appropriate pair of quantization parameters for texture and depth views to maximize the synthesized view quality subject to a fixed total bit rate. In this paper we propose a scalable bit-allocation scheme, where a single ordering of texture and depth packets is derived and used to obtain optimal bit allocation between texture and depth views for any total target rates. In the proposed scheme, both texture and depth views are encoded using the quality scalable coding method; that is, medium grain scalable (MGS) coding of the Scalable Video Coding (SVC) extension of the Advanced Video Coding (H.264/AVC) standard. For varying target total bit rates, optimal bit truncation points for both texture and depth views can be obtained using the proposed scheme. Moreover, we propose to order the enhancement layer packets of the H.264/SVC MGS encoded depth view according to their contribution to the reduction of the synthesized view distortion. On one hand, this improves the depth view packet ordering when considered the rate-distortion performance of synthesized views, which is demonstrated by the experimental results. On the other hand, the information obtained in this step is used to facilitate optimal bit allocation between texture and depth views. Experimental results demonstrate the effectiveness of the proposed scalable bit-allocation scheme for texture and depth views.

BackgroundPrincipal component analysis (PCA) has been widely employed for automatic neuronal spike sorting. Calculating principal components (PCs) is computationally expensive, and requires complex numerical operations and large memory resources. Substantial hardware resources are therefore needed for hardware implementations of PCA. General Hebbian algorithm (GHA) has been proposed for calculating PCs of neuronal spikes in our previous work, which eliminates the needs of computationally expensive covariance analysis and eigenvalue decomposition in conventional PCA algorithms. However, large memory resources are still inherently required for storing a large volume of aligned spikes for training PCs. The large size memory will consume large hardware resources and contribute significant power dissipation, which make GHA difficult to be implemented in portable or implantable multi-channel recording micro-systems.MethodIn this paper, we present a new algorithm for PCA-based spike sorting based on GHA, namely stream-based Hebbian eigenfilter, which eliminates the inherent memory requirements of GHA while keeping the accuracy of spike sorting by utilizing the pseudo-stationarity of neuronal spikes. Because of the reduction of large hardware storage requirements, the proposed algorithm can lead to ultra-low hardware resources and power consumption of hardware implementations, which is critical for the future multi-channel micro-systems. Both clinical and synthetic neural recording data sets were employed for evaluating the accuracy of the stream-based Hebbian eigenfilter. The performance of spike sorting using stream-based eigenfilter and the computational complexity of the eigenfilter were rigorously evaluated and compared with conventional PCA algorithms. Field programmable logic arrays (FPGAs) were employed to implement the proposed algorithm, evaluate the hardware implementations and demonstrate the reduction in both power consumption and hardware memories achieved by the streaming computingResults and discussionResults demonstrate that the stream-based eigenfilter can achieve the same accuracy and is 10 times more computationally efficient when compared with conventional PCA algorithms. Hardware evaluations show that 90.3% logic resources, 95.1% power consumption and 86.8% computing latency can be reduced by the stream-based eigenfilter when compared with PCA hardware. By utilizing the streaming method, 92% memory resources and 67% power consumption can be saved when compared with the direct implementation of GHA.ConclusionStream-based Hebbian eigenfilter presents a novel approach to enable real-time spike sorting with reduced computational complexity and hardware costs. This new design can be further utilized for multi-channel neuro-physiological experiments or chronic implants.

Optical interconnects for system-in-package applications can be designed for various bit rates. In this paper, an optimization study is conducted to find the optimal parameters for electrooptical links, based on a silicon photonic technology. We focus on the bit rate to achieve highest possible power efficiencies. This paper takes all the elements of an electrooptical link into account: serialization stage, ring-resonator-based modulator, thermal stabilization, modulator driver, laser, receiver, deserialization stage, and clock-phase generation. The optimization is based on a simulation-supported database for single-ended transimpedance amplifiers (TIAs). For all the other, elements of the link simulation-based power consumption models are presented. Furthermore, an analytical solution for the TIA bandwidth and bit rate relationship is derived based on the system jitter, the TIA noise, transimpedance, bandwidth and minimal output swing, and the available input signal. Optimal bit rates are derived and discussed for a 65-nm CMOS and a 28-nm fully depleted silicon-on-insulator technology. We found that the optimal bit rates increase with more aggressive technology scaling and smaller photodiode capacitances, but decrease if lower static power consumptions can be achieved (e.g., by efficient thermal tuning of ring-resonator modulators). We conclude that further research should aim for lower tuning powers instead of higher speed.

Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital very-large-scale-integration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand high-speed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of high-end products to keep power under control, due to the increased costs of packaging and cooling this type of device. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of low-power VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature.

Big-data storage poses significant challenges to anonymization of sensitive information against data sniffing. Not only will the encryption bandwidth be limited by the I/O traffic, the transfer of data between the processor and the memory will also expose the input-output mapping of intermediate computations on I/O channels that are susceptible to semi-invasive and non-invasive attacks. Limited by the simplistic cell-level logic, existing logic-in-memory computing architectures are incapable of performing the complete encryption process within the memory at reasonable throughput and energy efficiency. In this paper, a block-level in-memory architecture for advanced encryption standard (AES) is proposed. The proposed technique, called DW-AES, maps all AES operations directly to the domain-wall nanowires. The entire encryption process can be completed within a homogeneous, high-density, and standby-power-free non-volatile spintronic-based memory array without exposing the intermediate results to external I/O interface. Domain-wall nanowire-based pipelining and multi-issue pipelining methods are also proposed to increase the throughput of the baseline DW-AES with an insignificant area overhead and negligible difference on leakage power and energy consumption. The experimental results show that DW-AES can reduce the leakage power and area by the orders of magnitude compared with existing CMOS ASIC accelerators. It has an energy efficiency of 22 pJ/b, which is $5\times $ and $3\times $ better than the CMOS ASIC and memristive CMOL-based implementations, respectively. Under the same area budget, the proposed DW-AES achieves $4.6\times $ higher throughput than the latest CMOS ASIC AES with similar power consumption. The throughput improvement increases to $11\times $ for pipelined DW-AES at the expense of doubling the power consumption.

In this article the spread and iterative search (S&IS) and the low density and iterative search (LD&IS) motion estimation algorithms are presented. The proposed algorithms are hardware-friendly because they have a regular number of cycles to encode a block, they have a regular memory access and the parallelism can be better explored when compared to other published solutions. The proposed algorithms were evaluated under the high efficiency video coding reference software and compared with the state-of-art enhanced predictive zonal search (EPZS) algorithm and with the well know diamond search (DS) algorithm. The designed algorithms presented better BD-rate results than DS but they presented some losses when compared to EPZS. Since EPZS is not focused in a hardware design, it presents a lot of data dependencies, a irregular memory access, a non-deterministic number of operations to encode a block and it must store motion vectors of previously encoded frames. All these features are undesirable for many applications, including those ones focused on battery powered devices. To show the efficiency of the proposed algorithms, two architectures were designed targeting these algorithms and they were synthesized for Altera Stratix 4 and for ASIC using TSMC 90 nm standard-cells technology. Synthesis results show that the architectures are capable to process HD 1080p videos, at real time, by obtaining good results in terms of hardware resources use, power consumption and processing rate when compared to related works. The ASIC implementations are able to guarantee real-time performance for high definition videos consuming 12.5 and 13.5 mW, respectively. These results are possible because S&IS and LD&IS were developed focusing on hardware design.

The Internet of Things (IoT) has seen rapid advancements and widespread deployment of wireless devices recently. To pursue the long-term deployment goal of the Internet of Things, a lot of work in recent years has focused on low-power devices, such as backscatter systems. However, they face two key challenges, unequal uplink and downlink communication range, and weak end devices’ inability to handle downlink conflicts and networking. In this paper, we propose a µW-level downlink receiving system, which enhances the anti-interference and anti-conflict capabilities of low-power end devices. We also present a state machine model for networking capabilities. We implemented the prototype system using discrete components and FPGA and conducted experiments. The result shows that our system achieves a downlink communication range of over 250m at a 1kbps data rate with 1% BER and increased by more than 10 times compared to conventional backscatter receivers. The power consumption is 73.6 µW.

Video applications are an important part of mobile devices. Capacity of battery is increasing maximum of 10 percentage per year, which may not be sufficient for upcoming application and operating system. Power consumption by video application depends on factors like network load, signal quality, bandwidth and it can be optimized through heuristics based streaming. The work presented here exploits adaptive bitrate streaming to determine the optimum bitrate for available bandwidth. Selection of optimum bitrate ensures quality delivery of video as well as optimum power consumption of the device. Moving Picture Expert Group - Dynamic Adaptive Streaming over HTTP (MPEG-DASH) has been used for implementing the switching between the bitrates. The fifteen bitrates selected for encoding are closer to the mean value which is available for streaming. The approach has been tested on an Android based tablet over thirty videos to check the dependency of the factors on each other. This is the major approach to establish relationship between bitrate and power consumption for video streaming. The result obtained shows a 14 percentage of power saving with minimum buffering and good quality of service.

Approximate computing is a promising approach in the design of low-power digital systems. There are two main approaches in approximate computing: the first relies on lowering the supply voltage level on specific computational blocks, while the second relies on completely truncating specific computational blocks. The second option is more aggressive; however, it is deterministic and leads to better energy savings. This paper, in accordance with the second option, presents a set of 8-bit combinational digital multipliers that provide an approximate product while reducing energy consumption by up to 57% while maintaining excellent results, as demonstrated by several image-processing applications.

Energy-efficient compact alternatives to fully digital computing strategies could be achieved by implementations of artificial neural networks (ANNs) that borrow analog techniques. In-memory computing based on crossbar device architectures with memristive materials systems that execute, in an analog way, multiply-and-accumulate operations prevalent in ANN is a notable example. Ferroelectric (FE) materials are promising candidates for achieving ANN thanks to their excellent down-scalability, improved electrical control, and high energy efficiency. However, it remains challenging to develop a crossbar device architecture using FE materials. The difficulty stems from decreasing the leakage current of FE hardware and, simultaneously, reducing the film thickness for achieving compact systems. Here, we have performed density-functional-theory calculations to investigate the electronic, energy-based, and structural signatures of wurtzite FE material Al0.75Sc0.25N with a nitrogen vacancy (VN) in different charge states. We find that VN can introduce two defect states, viz., the singlet state above the valence band maximum (VBM) and a triplet state below the conduction band minimum in wurtzite AlScN models. The calculations reveal that the group of transition levels E3+/2+/E2+/1+ with small formation energies occur at ∼0.78/1.03 eV above the VBM in the wurtzite AlScN with a relaxed configuration, which may shift by a large degree to lower energy levels if atoms surrounding the defect are not fully relaxed. Theoretical studies elucidate the vacancy-enhanced increase in the leakage current utilizing large AlScN supercells. These findings render atomistic insights that can provide a path forward for the design of next-generation portable low-power electronic systems.

This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120µm2) single p-well (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. The results from a 140kb programmable dynamic SRAM characterization test module provide both information about location and cause of failures as well as power and performance by mimicking system operating conditions over a wide supply voltage range. A 410mV minimum operating voltage and less than 310mV data retention voltage with a leakage current close to 100fA/bitcell are measured. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.