Dynamic Power Management and Dynamic Voltage Scaling in Real-time CMP Systems

The functionality of embedded systems is ever growing. The computational power of embedded systems is growing to match this demand, with embedded multiprocessor systems becoming more common. The limitations of embedded systems are not always related to chip size but are commonly due to energy and/or power constraints. While it can be possible to embed a more powerful Multiprocessor System on Chip (MPSoC), it is not always possible to provide an energy or power supply that meets its demands within the device’s size and weight requirements. Power management through Dynamic Voltage and Frequency Scaling (DVFS) enables the device to be run at less than its maximum voltage and frequency, allowing high computational capability when necessary while conserving power at other times. Embedded systems commonly perform real-time functionality. A real-time application has an associated formal model to verify that it meets its timing requirements. This formal model is used to perform a worst-case timing analysis to ensure that the application meets its requirements. These models incorporate the worst-case timing of the application’s computation and communication. Timing changes due to power management must also be taken into account, complicating the verification process. The drive for evermore functionality has led to mixed time-criticality systems, in which multiple applications of various timing criticalities share the same (hardware) resources. This complicates the verification process further as the timing interference due to shared resource contention must be taken into account. A monolithic verification effort is therefore traditionally required after system integration and must be carried out again if any modifications are made that affect the timing of any of the applications. The problem that we aim to solve in this work is to enable real-time applications to perform independent execution and power management without violating their timing requirements or invalidating the timing verification of concurrently executing applications. To solve this problem, we contribute the Composable and Predictable Microkernel (CoMik) to composably and predictably virtualise processors. When used in combination with composable and predictable memory controllers and interconnect (as provided by the Composable and Predictable System-on-Chip (CompSOC) platform), these virtual processors cannot interfere with each other’s timing by even a single cycle. If whatever executes on the virtual processors (e.g. an Operating System (OS) or an application directly) has a real-time requirement, it can be verified independently of whatever executes on the concurrent virtual processors and other virtual resources. To enable formally analysable application execution, we contribute the Predictable Operating System (POSe) that enables dataflow applications to be executed on the (virtualised) processor. We contribute a combined application and platform dataflow graph, including an algorithm to automate this process. When annotated with worst-case timings, the combined application and system graph is then used to verify that the application meets its timing requirement. If the application’s performance is better than its requirement (e.g. when the input or platform behaviour are better than worst case), its performance can be reduced using DVFS to achieve a reduction in power consumption. We contribute an off-line convex optimisation that uses the combined application and platform dataflow model to derive static run-time operating frequency levels to achieve low power consumption. The off-line technique is able to exploit static slack in the schedule, but not dynamic run-time slack due to variations in task execution times. Before dynamic slack can be used it must be possible to observe it. For this purpose, CoMik provides independent power, energy and timing accounting per virtual processor. This enables each virtual processor to be assigned individual power and energy budgets and POSe applications to be assigned timing budgets. We contribute a description and model of how energy and power budgets can be distributed between multiple virtual processors, enabling whatever executes on the virtual processor to perform composable independent power-management without affecting the ability of other virtual processors from using their entire budget allocation. Using CoMik’s accounting infrastructure, we also demonstrate how the quality of applications can be dynamically scaled to assist meeting timing, energy or power requirements. We further contribute a distributed dynamic power management policy that enables dataflow applications that are mapped onto multiple (virtual) processors to make distributed dynamic slack observations and local power-management decisions. We demonstrate the applicability of the presented techniques on an implemented Field Programmable Gate Array (FPGA) prototype of a CompSOC hardware platform instance, using an H.263 decoder as a case-study application. We show that our techniques do not only work in theory, but that they are also implementable and implemented.

To reduce the power consumption of portable devices, many researches have been conducted on the dynamic voltage scaling(DVS) and dynamic power management(DPM). Embedded systems such as DMBs, PMPs and PDAs require long battery life without reducing their performance. Also, power consumption is the most important factor in ubiquitous environment. Most researches are focused on power saving methods by hardware circuits. One of them is DVS, which has proven as a highly effective technique to reduce dynamic power consumption. But, software design and control should be considered to minimize the total energy consumption. This paper presents a power management design and implementation for embedded multimedia systems by guaranteeing QoS. The implemented results show that the system saves the total power consumption up to 5% compared with the DVS on the experiment board.

In this paper, we focus on joint energy and performance optimization for streaming applications on multiprocessor systems-on-chip by combining task-level coarse-grained software pipelining with DVS (dynamic voltage scaling)and DPM (dynamic power management) techniques with the considerations of transition overhead, inter-processor communication and discrete voltage levels. We propose a two-phase approach to solve the problem. In the first phase, we propose a coarse-grained task parallelization algorithm called RDAG to transform a periodic dependent task graph into a set of independent tasks based on the retiming technique[19]. In the second phase, we propose a novel scheduling algorithm called SpringS that works like a spring by iteratively adjusting task scheduling and voltage selection by combining DVS and DPM. We conduct experiments with a set of benchmarks from E3S [10] and TGFF [27]. The experimental results show that our technique can achieve 49:8% energy saving on average compared with the approach in [20], that applied DVS and DPM without software pipelining. In addition, given a tight timing constraint, our technique can obtain a feasible solution while the approach in [20] cannot.

Stochastic DVS-based dynamic power management for soft real-time systems

Reducing the power consumption while maintaining the response time constraint has been an important goal in server system design. One of the techniques widely explored in the literature to achieve this goal is Dynamic Voltage Scaling (DVS). However, DVS is not efficient in modern systems where the overall power consumption includes a large portion of static power consumption. In this paper, we aim to reduce the static power consumption by Dynamic Power Management (DPM) with sleep model in addition to DVS. We propose a smart PowerSleep power-saving scheme, where a procrastination technique is adopted to carefully aggregate jobs to reduce the overhead of transitions in and out of the sleep mode. We also observe that PowerSleep might not always be a good choice due to the mode transition overhead when the server utilization is high, where instead we use PowerIdle power-saving scheme with DVS only. By modeling the system with M/G/1/PS queuing model and further extensions, we present how to minimize the mean power consumption of the server under the given mean response time constraint for both power-saving schemes. Simulation results show that our smart PowerSleep scheme significantly outperforms the simple power saving scheme which adopts sleep mode.

Energy is a major concern when designing real-time systems. A common method for saving energy while still guaranteeing the real-time constraints is to embed dynamic voltage and frequency scaling (DVFS) mechanisms and dynamic power management (DPM) mechanisms within a real-time scheduling algorithm such as EDF. This paper proposes a new extension to the EDF scheduler, termed energy oriented EDF (EO-EDF). The new scheduler makes it possible to change the original EDF task execution order to better utilise the slack time and thus decrease the energy consumption, while still meeting the task deadlines. The new task order is defined according to a novel criterion we invented, termed task prediction order (TPO). The paper introduces two new versions of the EO-EDF scheduler, termed TPO-EDF and STPO-EDF. While STPO-EDF applies the TPO criterion in a static manner, TPO-EDF allows it to be used dynamically. We simulate the new proposed algorithms using both synthetic workloads and real-time benchmarks. The evaluations show that integrating both the TPO-EDF and STPO-EDF scheduling algorithms with DVFS and DPM mechanisms achieves an energy savings of 30% on average, in comparison with current known EDF based scheduling utilising DVFS and DPM mechanisms.

There is a consensus that exascale systems should operate within a power envelope of 20MW. Consequently, energy conservation is still considered as the most crucial constraint if such systems are to be realized.

Modern real-time embedded systems have increasingly penetrated our daily life and are also often constrained in terms of temperature and energy. In this paper, a thesis is defended that from a real-time systems perspective, thermally constrained dynamic power management approaches behave very similar to idealised dynamic voltage and frequency scaling. Hence, existing dynamic voltage and frequency scaling solutions proposed for periodic/sporadic task models can be applied to thermally constrained dynamic power management systems with moderate effort. This work presents the similarities along with the distinctive elements between two approaches. Within the case study, the porting of a dynamic voltage and frequency scaling algorithm of the literature to thermally constrained dynamic power management system is demonstrated.

Distributed architectures with fixed-priority scheduling using Dynamic Power Management (DPM) for CPU optimization are one of the serious concerns in INTEL PXA270. Increasing the number of transistors and task mapping on chips causes greater energy dissipation and power consumption. This study addresses the issue of system-level higher CPU energy dissipation during the execution of parallel workloads with common deadlines by introducing a framework that includes task migration based on DPM and an Adaptive Deadline First scheduling (A-DF) scheme to properly schedule migratable tasks. The DPM policy and efficient task allocation and scheduling using A-DF enhance overall throughput and optimize energy consumption to avoid delays and performance degradation in multiprocessor systems. The proposed model assigns processors to the ready task set to meet deadline requirements. A full task migration policy is also integrated to ensure proper task mapping and interprocess linkage among tasks with the same deadlines. The execution of a task can pause on one CPU and reschedule execution on another to avoid delay and ensure that the deadline is met. The proposed method shifts the context of the task from running to sleep and from idle to sleep using an adaptive DPM approach. The proposed scheme showed a promising reduction in energy dissipation compared to other conventional energy-aware task migration techniques. Simulations were conducted using a super pipelined microarchitecture Intel XScale PXA270 using instruction and data cache per core of 32 Kbyte I-cache and 32 Kbyte D-cache on various utilization factors (ui) of 18% and 20%. The proposed approach consumed 6.3% less energy and achieved 2.1% and 2.4% improvements in terms of accuracy and precision when almost half of the CPU is running, and on a lower workload consumed 1.04% less energy. The proposed design provided significant improvements in clock rates of 100, 104, and 116 MHz.

Power-aware fixed priority scheduling for sporadic tasks in hard real-time systems

Cyber Physical Systems are composed of many embedded systems which monitor and control the physical processes for tight integrations of computation and physical processes. Such embedded systems require not only real-time capabilities but also high throughput and low power consumption. High throughput is mainly achieved by parallel architectures such as Simultaneous Multithreading (SMT) and Chip Multiprocessor (CMP), and low power consumption is mainly achieved by Real-Time Dynamic Voltage and Frequency Scaling (RT-DVFS) under the real-time constraint. In this paper, we present a RT-DVFS algorithm called Hetero Efficiency to Logical Processor (HeLP) which can reduce power consumption easily and effectively in prioritized SMT processors. We also present Hetero Efficiency to Logical Processor with Temporal Migration (HeLP-TM) which applies the temporal migration technique to HeLP. Simulation results show that HeLP can reduce power consumption effectively and HeLPTM is more effective than HeLP.

In this paper, we propose a novel accuracy-reconfigurable stochastic computing (ARSC) framework for dynamic reliability and power management. Different than the existing stochastic computing works, where the accuracy versus power/energy trade-off is carried out in the design time, the new ARSC design can change accuracy or bit-width of the data in the run-time so that it can accommodate the long-term aging effects by slowing the system clock frequency at the cost of accuracy while maintaining the throughput of the computing. We validate the ARSC concept on a discrete cosine transformation (DCT) and inverse DCT designs for image compressing/decompressing applications, which are implemented on Xilinx Spartan-6 family XC6SLX45 platform. Experimental results show that the new design can easily mitigate the long-term aging induced effects by accuracy trade-off while maintaining the throughput of the whole computing process using simple frequency scaling. We further show that one-bit precision loss for the input data, which translated to 3.44dB of the accuracy loss in term of Peak Signal to Noise Ratio (PSNR) for images, we can sufficiently compensate the NBTI induced aging effects in 10 years while maintaining the pre-aging computing throughput of 7.19 frames per second. At the same time, we can save 74% power consumption by 10.67dB of accuracy loss. The proposed ARSC computing framework also allows much aggressive frequency scaling, which can lead to order of magnitude power savings compared to the traditional dynamic voltage and frequency scaling (DVFS) techniques.

The usage of interactive applications increases in handheld systems. In this paper, we describe a system-level dynamic power management scheme that considers interaction between the CPU and the WNIC, and interactive applications to reduce the energy consumption of handheld systems. Previous research efforts considered the CPU and the WNIC separately to reduce energy consumption. The proposed scheme reduces the energy consumption of handheld systems by using the information gathered from the WNIC to control the CPU voltage and frequency when interactive applications are executed. Experimental results show that on average the proposed scheme reduces energy consumption by 46% when compared to DVFS (Dynamic Voltage and Frequency Scaling) for the CPU and DPM (Dynamic Power Management) for the WNIC.

The architectures of large-scale Internet servers are becoming more complex each year in order to store and process a large amount of Internet data (Big Data) as efficiently as possible. One of the consequences of this continually growing complexity is that individual servers consume a significant amount of data even when they are idle. In this paper we experimentally investigate the scope and usefulness of existing and proposed dynamic power management strategies to manage power at core, socket, and server levels. Our experiment involves four dynamic voltage and frequency scaling policies, three different workloads having different resource consumption statistics, and the activation and deactivation of different sockets (packets) of a multicore, multi-socket server. Moreover, we establish a quantitative relationships between the workload (w) and the estimated power consumption (p) under different power management strategies to make a quantitative comparison of the different strategies and server configurations.

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.KeywordsExecution TimeSupply VoltageKnapsack ProblemBasic BlockProgram RegionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.