Power Saving Design for Servers under Response Time Constraint

To reduce the power consumption of portable devices, many researches have been conducted on the dynamic voltage scaling(DVS) and dynamic power management(DPM). Embedded systems such as DMBs, PMPs and PDAs require long battery life without reducing their performance. Also, power consumption is the most important factor in ubiquitous environment. Most researches are focused on power saving methods by hardware circuits. One of them is DVS, which has proven as a highly effective technique to reduce dynamic power consumption. But, software design and control should be considered to minimize the total energy consumption. This paper presents a power management design and implementation for embedded multimedia systems by guaranteeing QoS. The implemented results show that the system saves the total power consumption up to 5% compared with the DVS on the experiment board.

Real-time embedded systems need reducing power consumption while still maintaining high performance. Dynamic power management (DPM) and dynamic voltage scaling (DVS) are effective control techniques to reduce the energy consumption. We present a real-time energy saving scheduling (RESS) algorithm using DPM and DVS to reduce the energy cost for chip multiprocessor (CMP) systems. The simulating experiment results indicate that our algorithm can save system energy cost with little system performance degradation.

In this paper, we focus on joint energy and performance optimization for streaming applications on multiprocessor systems-on-chip by combining task-level coarse-grained software pipelining with DVS (dynamic voltage scaling)and DPM (dynamic power management) techniques with the considerations of transition overhead, inter-processor communication and discrete voltage levels. We propose a two-phase approach to solve the problem. In the first phase, we propose a coarse-grained task parallelization algorithm called RDAG to transform a periodic dependent task graph into a set of independent tasks based on the retiming technique[19]. In the second phase, we propose a novel scheduling algorithm called SpringS that works like a spring by iteratively adjusting task scheduling and voltage selection by combining DVS and DPM. We conduct experiments with a set of benchmarks from E3S [10] and TGFF [27]. The experimental results show that our technique can achieve 49:8% energy saving on average compared with the approach in [20], that applied DVS and DPM without software pipelining. In addition, given a tight timing constraint, our technique can obtain a feasible solution while the approach in [20] cannot.

The functionality of embedded systems is ever growing. The computational power of embedded systems is growing to match this demand, with embedded multiprocessor systems becoming more common. The limitations of embedded systems are not always related to chip size but are commonly due to energy and/or power constraints. While it can be possible to embed a more powerful Multiprocessor System on Chip (MPSoC), it is not always possible to provide an energy or power supply that meets its demands within the device’s size and weight requirements. Power management through Dynamic Voltage and Frequency Scaling (DVFS) enables the device to be run at less than its maximum voltage and frequency, allowing high computational capability when necessary while conserving power at other times. Embedded systems commonly perform real-time functionality. A real-time application has an associated formal model to verify that it meets its timing requirements. This formal model is used to perform a worst-case timing analysis to ensure that the application meets its requirements. These models incorporate the worst-case timing of the application’s computation and communication. Timing changes due to power management must also be taken into account, complicating the verification process. The drive for evermore functionality has led to mixed time-criticality systems, in which multiple applications of various timing criticalities share the same (hardware) resources. This complicates the verification process further as the timing interference due to shared resource contention must be taken into account. A monolithic verification effort is therefore traditionally required after system integration and must be carried out again if any modifications are made that affect the timing of any of the applications. The problem that we aim to solve in this work is to enable real-time applications to perform independent execution and power management without violating their timing requirements or invalidating the timing verification of concurrently executing applications. To solve this problem, we contribute the Composable and Predictable Microkernel (CoMik) to composably and predictably virtualise processors. When used in combination with composable and predictable memory controllers and interconnect (as provided by the Composable and Predictable System-on-Chip (CompSOC) platform), these virtual processors cannot interfere with each other’s timing by even a single cycle. If whatever executes on the virtual processors (e.g. an Operating System (OS) or an application directly) has a real-time requirement, it can be verified independently of whatever executes on the concurrent virtual processors and other virtual resources. To enable formally analysable application execution, we contribute the Predictable Operating System (POSe) that enables dataflow applications to be executed on the (virtualised) processor. We contribute a combined application and platform dataflow graph, including an algorithm to automate this process. When annotated with worst-case timings, the combined application and system graph is then used to verify that the application meets its timing requirement. If the application’s performance is better than its requirement (e.g. when the input or platform behaviour are better than worst case), its performance can be reduced using DVFS to achieve a reduction in power consumption. We contribute an off-line convex optimisation that uses the combined application and platform dataflow model to derive static run-time operating frequency levels to achieve low power consumption. The off-line technique is able to exploit static slack in the schedule, but not dynamic run-time slack due to variations in task execution times. Before dynamic slack can be used it must be possible to observe it. For this purpose, CoMik provides independent power, energy and timing accounting per virtual processor. This enables each virtual processor to be assigned individual power and energy budgets and POSe applications to be assigned timing budgets. We contribute a description and model of how energy and power budgets can be distributed between multiple virtual processors, enabling whatever executes on the virtual processor to perform composable independent power-management without affecting the ability of other virtual processors from using their entire budget allocation. Using CoMik’s accounting infrastructure, we also demonstrate how the quality of applications can be dynamically scaled to assist meeting timing, energy or power requirements. We further contribute a distributed dynamic power management policy that enables dataflow applications that are mapped onto multiple (virtual) processors to make distributed dynamic slack observations and local power-management decisions. We demonstrate the applicability of the presented techniques on an implemented Field Programmable Gate Array (FPGA) prototype of a CompSOC hardware platform instance, using an H.263 decoder as a case-study application. We show that our techniques do not only work in theory, but that they are also implementable and implemented.

Shrinking feature sizes, reduced voltages, and higher transistor count of nano-scale silicon chips challenge designers in terms of performance, power consumption, and reliability. This paper investigates the effect of simultaneous use of dynamic voltage and frequency scaling (DVFS) and body biasing (BB) on power consumption, reliability, and performance. An analytical model of reliability as a function of body bias voltage, supply voltage, and frequency is proposed. We derive a three dimensional optimization problem by exploiting proposed reliability model in conjunction with power consumption and performance model. The resulting problem is solved using widely-used geometric optimization to identify optimal supply voltage and body bias voltage and then is validated using accurate simulation. Afterwards, it is demonstrated how joint energy-performance-reliability space optimization method can be used in an adaptive reliability-aware power management systems. Finally, we show that combined soft error aware BB and DVFS is capable of improving power consumption about 30% in comparison to reliability-aware DVFS only for the same level of reliability and performance constraints.

When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however, static power consumption is expected to increase significantly. Then it will be more effective to limit the number of employed processors, and use a combination of DVS and processor shutdown. Scheduling heuristics are presented that determine the best trade-off between these three techniques: DVS, processor shutdown, and finding the optimal number of processors. Experimental results show that our approach reduces the total energy consumption by up to 25% for tight deadlines and by up to 57% for loose deadlines compared to DVS.We also compare the energy consumed by our scheduling algorithm to two lower bounds, and show that our best approach leaves little room for improvement.

As the computing environments are continuously moving towards battery-operated mobile and handheld systems, the development of energy-saving mechanisms for such devices has recently become a technical challenge. Dynamic voltage scaling (DVS) has historically been considered an effective method to reduce the processor power consumption. Conventional DVS techniques typically consider only processor utilisation issues in a policy-making process. However, as memory-bound multimedia applications are becoming popular in handheld devices, the DVS policies should consider the so-called ‘memory wall’ problem to maximise energy gain. Recent DVS techniques suffer from the inefficiency of their policies caused by the memory-wall problem while executing multimedia applications, and no previous research on DVS considers the problem explicitly. The existence of the memory wall problem in a real system is revealed and a metric that can be used to detect the problem in advance is found. A memory-aware DVS (M-DVS) technique that takes the memory wall problem fully into consideration is proposed. The experimental results on a PDA show that M-DVS can reduce ∼8% of additional power consumption, compared with conventional DVS, without any QoS degradation for handling multimedia clips.

In this paper, we propose a novel accuracy-reconfigurable stochastic computing (ARSC) framework for dynamic reliability and power management. Different than the existing stochastic computing works, where the accuracy versus power/energy trade-off is carried out in the design time, the new ARSC design can change accuracy or bit-width of the data in the run-time so that it can accommodate the long-term aging effects by slowing the system clock frequency at the cost of accuracy while maintaining the throughput of the computing. We validate the ARSC concept on a discrete cosine transformation (DCT) and inverse DCT designs for image compressing/decompressing applications, which are implemented on Xilinx Spartan-6 family XC6SLX45 platform. Experimental results show that the new design can easily mitigate the long-term aging induced effects by accuracy trade-off while maintaining the throughput of the whole computing process using simple frequency scaling. We further show that one-bit precision loss for the input data, which translated to 3.44dB of the accuracy loss in term of Peak Signal to Noise Ratio (PSNR) for images, we can sufficiently compensate the NBTI induced aging effects in 10 years while maintaining the pre-aging computing throughput of 7.19 frames per second. At the same time, we can save 74% power consumption by 10.67dB of accuracy loss. The proposed ARSC computing framework also allows much aggressive frequency scaling, which can lead to order of magnitude power savings compared to the traditional dynamic voltage and frequency scaling (DVFS) techniques.

Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to reduce the power consumption. By using this method, we manage to save power by up to 45.7% compared to a baseline architecture without any performance loss.

Increasing speed and complexity of design gives a significant increase in power consumption in VLSI chips. Speed, power consumption and space are major issues in VLSI circuit. To meet these challenges there are certain design techniques which are used to reduce power. Optimization of power can be done by considering various components such as transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, power gating, long channel transistor, stacking & parking states and logic styles etc. Power consumption in VLSI circuit is data dependent. In this paper different design methods are tested to optimize the power. It is found that algorithm based design reduces gate switching activity that results reduction of power in multiplier circuit. Keyword: Transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking & parking states, logic styles, Genetic algorithm, Booth multiplication I. Introduction Reduction in power dissipation is an important design issue in VLSI circuits. The design parameters have major effect on the overall performance of the system. On the basis of component used and their function different optimization techniques can be used. For example in case of multiplier power consumption depends upon data. This is because switching contributes to more power consumption. This can be optimized by using various gate combinations. Gate switching can be reduced by using algoritms. For example of in case of multiplier design method Booth algorithm as well as modified Booth algorithm can be used for efficient multiplication. In this paper various approaches are used for power consumption eg. transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking& parking states, logic styles, Genetic algorithm, Booth multiplication etc. This paper is divided into five sections. First section is of introduction. Second section is about preliminary studies. Third section includes different design methods and their testing. Fourth section is of comparison with discussion. Finally, fifth section is conclusion of the work reported here.

Stochastic DVS-based dynamic power management for soft real-time systems

Innovative system-level computer-aided design techniques are required for optimizing the performance and power of applications that are mapped to multiprocessor system-on-chip (SoC) architectures. The paper addresses the hitherto unexplored problem of system-level low power design of multimedia and network processing applications with deadline greater than period. This paper presents four techniques that combine low power optimizations (namely dynamic voltage and frequency scaling (DVS) and dynamic power management (DPM)) with loop transformations (functional pipelining and unrolling) to minimize the power consumption, while satisfying the period and deadline constraints of the application. The strengths of the techniques lie in their low complexity and large power consumption savings when compared with existing heuristic based approaches, and close to optimum results when compared with our ILP based approach (presented elsewhere stated in K. Srinivasan and K.S. Chatha (2004)). All our techniques result in large system-level power reductions when compared with existing heuristic approaches (max: 55.45%, min: 28.60%, ave: 42.02%). Further, the results produced by our deterministic and stochastic techniques for realistic benchmarks are on an average within 12.07% and 4.125%, respectively of the optimum solution produced by the ILP based approach. Our heuristic techniques are faster than the ILP based approach by several orders of magnitude.

—The rapid advancement of mobile technologies has led to increasingly powerful and feature-rich devices, yet this progress has also intensified the challenge of managing energy consumption effectively. Power optimization has therefore become a critical focus in mobile operating systems (OS), aiming to balance performance, functionality, and energy efficiency. As mobile devices integrate more complex hardware components and resource-intensive applications, ensuring sustainable power usage has become essential for improving battery life, user experience, and environmental sustainability. This research explores the fundamental question: How can mobile operating systems intelligently manage hardware and software resources to minimize power consumption without compromising performance or usability? To address this, the study examines key power optimization strategies and mechanisms integrated within modern mobile OS architectures, including Dynamic Voltage and Frequency Scaling (DVFS), power-aware CPU scheduling, Doze and App Standby modes, adaptive display and sensor management, and network optimization. The research also investigates the role of advanced techniques such as context-aware power management and machine learning-based predictive models in achieving dynamic, intelligent energy control. Using tools like Trepn Profiler, PowerTutor, and Android Battery Historian, the study evaluates how power consumption patterns can be analyzed and optimized in real time. The findings reveal that combining hardware-level techniques (like voltage scaling and clock gating) with software-level optimizations (such as adaptive scheduling and contextual awareness) results in significant energy savings while maintaining user satisfaction. Furthermore, the study highlights emerging challenges, including the trade-offs between performance and energy efficiency, the integration of AI for predictive optimization, and the need for sustainability across the device lifecycle. Ultimately, this research demonstrates that power optimization in mobile operating systems is not merely a technical requirement but a cornerstone of sustainable computing. Through intelligent power management, future mobile OSs can achieve greater efficiency, extended device longevity, and reduced environmental impact aligning technological innovation with eco-efficiency and user-centric design.

Energy is a major concern when designing real-time systems. A common method for saving energy while still guaranteeing the real-time constraints is to embed dynamic voltage and frequency scaling (DVFS) mechanisms and dynamic power management (DPM) mechanisms within a real-time scheduling algorithm such as EDF. This paper proposes a new extension to the EDF scheduler, termed energy oriented EDF (EO-EDF). The new scheduler makes it possible to change the original EDF task execution order to better utilise the slack time and thus decrease the energy consumption, while still meeting the task deadlines. The new task order is defined according to a novel criterion we invented, termed task prediction order (TPO). The paper introduces two new versions of the EO-EDF scheduler, termed TPO-EDF and STPO-EDF. While STPO-EDF applies the TPO criterion in a static manner, TPO-EDF allows it to be used dynamically. We simulate the new proposed algorithms using both synthetic workloads and real-time benchmarks. The evaluations show that integrating both the TPO-EDF and STPO-EDF scheduling algorithms with DVFS and DPM mechanisms achieves an energy savings of 30% on average, in comparison with current known EDF based scheduling utilising DVFS and DPM mechanisms.

Personal portable devices such as DMB (digital multimedia broadcasting)s, PMP (portable multimedia player)s and PDA (portable digital assistant)s require long battery life without reducing their performance. Power consumption is one of important factors in ubiquitous environments. To reduce the dynamic power consumption, many researches have been conducted on the dynamic voltage and frequency scaling (DVFS). DVFS can reduce the power consumption proportionally to the square of the supply voltage. But processor operation under the critical speed increases the leakage current. Larger leakage current increases the static power consumption. This paper proposes a new power-aware scheduling algorithm that reduces the static and dynamic power consumption to use frequency scaling between two discrete voltage levels and under the critical speed while meeting the deadline of given applications. The simulation and experimental implementation show that the proposed scheduling algorithm results in up to 25% energy gains over traditional DVFS algorithms with two task scheduling policies.