Dynamical effects of composite output capacitors on current‐mode controlled buck converter with constant current load

The P-V Curve, Q-V Curve, or P-Q-V Curve have been widely used to analyze power system behaviors under varying loading conditions. These curves have been generated under the condition that tire constant P-Q load component of a bus (or a collection of buses) varies, with the constant current load and constant impedance load being kept indeed As such, the physical meaning of these curves can be easily explained. Motivated by the facts that load models have profound impacts on power system behaviors and that the nonlinear load model ZIP-model is popular in modeling nonlinear behaviors of loads, this paper proposes a new class of curves, called ZIP-V curves, to better trace power system steady-state stationary behavior due to load and generation variations. The ZIP-V curves encompass the traditional P-V, Q-V, P-Q-V curves (constant P-Q load), I-V curve (constant current load), Z-V curve (constant impedance load), or generalized curves such as IP-V (constant current and constant power load), ZP-V (constant impedance and constant power load) or IZ-V (constant current and constant impedance load) curve when the values of corresponding components are kept constant. A tool based on the continuation power flow (CPFLOW) method useful for generating the ZIP-V curves is developed and its application to generate ZIP-V curves of a 4561-bus interconnected power system is illustrated.

DC link electrolytic capacitors are widely used in various PWM power converter system, such as adjustable speed driver(ASD) or DC/DC converter. Electrolytic capacitors, which is the most of the time affected by aging effect, plays a very important role for the power electronics system quality and reliability. This objective of this paper is to propose a improvement method to detect the rise of equivalent series resistor(ESR) in order to realize the online failure prediction of electrolytic capacitor for DC link of PWM power converter. The ESR detection scheme is based on the determination of the electrolytic capacitor AC losses calculated from voltage/current measurement using AC coupling. Therefore, the preposed online failure prediction method has the merits of easy ESR computation and circuit simplicity compare with BPF method. Simulation results show the veridity of the proposed on-line ESR estimation method.

Paolo Nora Paolo Nora, co-author of the paper “A novel sufficient condition to avoid sub-harmonic oscillations for Buck converters with constant on-time control” talks to us about their work page 305. I am part of the Architecture Definition Team of the Analogue Power and Interface Division (APID) of Microchip Technology Inc., and I collaborated with Profs. Bizzarri and Brambilla of the Politecnico di Milano on the topic of stable operation of Constant-ON-Time (COT) control, which is one of the most common control methods for analogue point-of-load (POL) Buck regulators. Indeed, my main area of interest is the architectural definition of analogue switch-mode regulators. A few years ago, I became aware of the topic of power integrity for my field of work. Both areas are very closely related, since POL regulators are often deployed in applications where power integrity considerations become increasingly critical for a successful power system design. The topic of Constant-ON-Time (COT) control, and – more generally – of ripple-based control of Buck converters has been a major focus for many power electronics researchers in the last few years, and different analysis methods have been used to determine its stability conditions. The importance of COT control (and its variations) of Buck POL converters is huge, due to the popularity of this control method in the industry. The reasons for such a wide popularity mainly stem from its superior load-transient performance over fixed-frequency architectures, and in the apparently simple design process it takes to develop the application. Simply put, the key design aspect is the phase relationship between the output voltage ripple fed to the controller and the Buck inductor current ripple. In addition, the total magnitude of the ripple seen by the controller plays an important role and must be adequate to ensure jitter-free operation. However, over many application cases encountered in practice, we've only seen a few of them being affected by confirmed instability issues (pulse-bursting operation) despite all recommended design practices being followed. This pushed us to consider different analysis methods to assess stability conditions, and here is where the nonlinear dynamical systems analysis expertise of profs. Bizzarri and Brambilla came to the fore. By using the state-variables methodology and state-plane graphical representations, and by leveraging nonlinear dynamical systems theory results, a new and more articulated sufficient condition for stable operation of the COT Buck converter was derived. This condition includes both circuit parameters and operating conditions. We have also shown that the well-known output capacitor time constant stability criterion is encompassed by the new sufficient condition. State-space analysis is a powerful method; however, its complexity rapidly explodes as the number of state variables increases. For the sake of manageability, the source of ripple fed to the COT control engine had to be limited to the resistor Re in series with the output capacitor, neglecting other well-known methods of ripple self-generation which would have added more state variables (i.e. more capacitors). The big question was then whether the simplified configuration would still be relevant from the practical perspective. Here is where some power integrity concepts, such as flat-impedance design of the POL stage and the power distribution network (PDN), played a key role. Indeed, resistor Re in series with the output capacitor may not just be a poorly controlled parasitic element – such as the equivalent series resistance (ESR) of an ordinary multi-layer ceramic capacitor (MLCC). In power-integrity-aware POL and PDN designs, the value of Re is intentionally controlled and – in some cases – it could even be implemented with a physical resistor. Also, if the POL stage is dedicated to some digital loads which are not particularly sensitive, the magnitude of the output voltage ripple generated by Re could also be adequate for a real-world application. We can conclude that the analysis of the simplified configuration presented in this Letter will become increasingly relevant as power integrity considerations will affect more and more POL/PDN designs. Another major challenge was experimental verification, whose description unfortunately exceeds the scope of the Letter. The state-variables method and the state-plane representation lend themselves very well to model rapid load transients and can predict the maximum load step that can be applied without saturating the COT control engine (i.e. engaging the minimum OFF time). This is also a new result and it is of utmost practical importance. Simply put, the outcome is that it should only take a very small load step to saturate the COT engine. If this does not happen, then it means that the design – for some reason – is not exploiting the full potential of COT control, and this should raise a red flag to the designer. As previously mentioned, this topic has attracted the attention of many researchers in power electronics over the last 10–15 years and there is a wealth of excellent, highly technical literature out there. I have to say that the perception of COT control is too simplistic for many practicing engineers: just make sure the controller is seeing enough voltage ripple, and that voltage ripple is in-phase with the inductor current ripple, and you're done! Unfortunately, experience reveals that the situation is not so simple. The challenge is how to convey all the highly technical results to a large community of users who simply do not have the time to dig into the fine details of POL design. The focus of many practicing engineers is not analogue design, not to mention POL design. Therefore, in the future, I see the highly technical analysis methods and results becoming available from the websites of many semiconductor vendors in the form of software tools as an extra aid for POL design verification, beyond the simple sets of equations provided by most datasheets. I also believe that the topic of digital implementation of COT-control and ripple-based control and their modeling will also grow exponentially.

Due to their substantial energy density and economical pricing, switching-mode power supplies (SMPSs) often utilize electrolytic capacitors. However, their ability to function at low temperatures is essential for dependable operation in several sectors, including telecommunications, automotive, and aerospace. This study includes an experimental evaluation of how well standard SMPS electrolytic capacitors operate at low temperatures. This paper investigates the suitability of standard electrolytic capacitors used in switched-mode power supplies (SMPSs) for low-temperature applications. The experimental evaluation exposed the capacitors to temperatures ranging from −5 °C to −40 °C, assessing capacitance (Cp), impedance (Z), dissipation factor (DF), and equivalent series resistance (ESR) at each temperature. The capacitor’s time-domain electrical signals were analyzed using the Pearson correlation coefficient to extract discriminative features. These features were input into an artificial neural network (ANN) for training and testing. The results indicated a significant impact of low temperatures on capacitor performance. Capacitance decreased with lower temperatures, while the ESR and leakage current increased, affecting stability and efficiency. Impedance was a valuable diagnostic tool for identifying potential capacitor failure, showing a 98.44% accuracy drop at −5 °C and 88.75% at the peak temperature, indicating proximity to the manufacturer’s specified limit. The study suggests further research and development to improve the performance of electrolytic capacitors in SMPS systems under cold conditions, aiming to boost efficiency and reliability.

Stability problems of DC Distributed Power System (DPS) arise with the widely use of tightly regulated power modules including: (i) negative impedance characteristic in small-signal sense of constant power load, (ii) the interaction among the power converters. The concept of impedance specifications for a stable DPS was introduced and explained. Electric Double-Layer Capacitor (EDLC) has high power density and small Equivalent Series Resistance (ESR). A viewpoint was brought forward originally in this paper that the output impedance of DC DPS will be reduced and system stability will be improved largely by linking EDLCs to the DC bus. It was proved valid and feasible in a design instance.

Electrolytic power capacitors have been widely used in power conversion system such as inverter or UPS because of characteristics of large capacitance, high-voltage and low-cost. The electrolytic capacitor, which is most of the time affected by the aging effect, plays a very important role for the power-electronics system quality and reliability. Therefore it is important to diagnosis monitoring the condition of an electrolytic capacitor in real-time to predict the failure. In this paper, the on-line remote diagnosis monitoring system for UPS DC link electrolytic capacitors using low-cost single-chip zigbee communication modules is developed. To estimate the health status of the capacitor, the equivalent series resistor(ESR) of the component has to be determined. The capacitor ESR is estimated by using RMS computation using BPF modeling of DC link ripple voltage/current. Zigbee-based hardware experimental results show that the proposed remote capacitor diagnosis monitoring system can be applied to UPS successfully. BR

An online condition monitoring method is presented for electrolytic capacitors health condition based on state observer method. With this method, both capacitance and equivalent series resistor in an electrolytic capacitor can be estimated online without disassembly from power converter systems. The method is with high precision without any additional hardware in application. The estimated capacitance and equivalent series resistor can be used to predict the rest useful life of the electrolytic capacitors and provide the suitable time for preventive maintenance. The method was verified by both simulation analysis and prototype testing. Experiment results shown a high precision results with relative error of less than 3%

The object of this paper is to present an economic electronic module integrated on an electrolytic capacitor that is able to indicate the moment when it must be changed. First, with a switchmode power supply as an example, the high probability of electrolytic capacitor failure with respect to other power components is noted. Second, the authors recall that the increase of the equivalent series resistance (ESR) of the capacitor is the best indicator of their faulty state. From the measurements of the voltage ripple and the capacitor current, one can deduce the ESR; the latter is compared to the ESR value of the sound capacitor deduced from the component case temperature. Thus, the capacitor deterioration can be diagnosed.

Electronic systems are becoming increasingly so-phisticated due to the emergence of advanced technology, which can produce robust integrated circuits by reducing the dimensions of transistors to just a few nanometers. Furthermore, most elec-tronic systems nowadays are in the form of system-on-chip and thus require stable voltage specifications. One of the critical elec-tronic components is the linear voltage regulator (LVR). LVRs are types of power converter used to maintain a stable and constant DC voltage to the load. Therefore, LVR stability is an essential aspect of voltage regulator design. The main factor influencing the stability of LVRs is the load disturbance. In general, disturbances such as a sudden change in load current can be compensated for by an output capacitor, which, contains a parasitic element known as equivalent series resistance (ESR). Therefore, the ESR and output capacitor specified in the datasheet is essential to compensate for load disturbance. However, LVR manufacturers typically do not provide detailed information, such as the internal physical parameters associated with the LVR in the datasheet. This situation leads to difficulties in identifying the behavior and stability of LVR. Therefore, this study aims to develop a method for estimating the internal physical parameters of LVR circuits that are difficult to measure directly by using a model-based approach (MBA). In this study, the MBA estimates the LVR model transfer function by analyzing the input and output signals via a linear regression method. Simulations through MATLAB and OrCAD Capture CIS software verify the estimated LVR model transfer function. Results show that the MBA has an excellent performance in estimating the physical parameters of LVRs and determining their stability.

This paper describes an automated test configuration that is used for rapid characterization of the equivalent series resistance (ESR) of ceramic multilayer capacitors. The primary components in this system are a coaxial resonant line, an HP 8753D vector network analyzer, and a personal computer. Sample measurements are provided for several 1206 style capacitors, and the trends in ESR versus the internal capacitor architecture are presented.

Multilayer ceramic capacitors (MLCC) have wide application in electronic due to its electrical characteristics: low equivalent series resistance (ESR) and high volume efficiency. One of the MLCC manufacturing problems is the choice of composition for the end pastes. The experimental results of the termination pastes composition influence on the quality high-voltage MLCC investigation are presented. The causes of the defects appearance in the termination are determined, the composition of the termination paste, which ensures the quality contact of the internal electrode with the external, is proposed.

In the traditional Constant-On-Time (COT) control mode, the output bypass capacitor mostly uses ceramic capacitors, and its equivalent series resistance (ESR) is small, the phase of output voltage ripple lags behind the inductor current, causing system instability. For this reason, this paper adopts the ripple compensation technology. By injecting the external ramp and the internal inductor current ramp, a virtual resistance is introduced for the ESR, and the resistance value of the ESR is increased to meet the stability conditions. The chip is designed based on 18V 0.1Sum BCD process. The simulation results show that when the input voltage is 12V and the temperature is 27°C, the system conversion efficiency can reach 97%, and the system output voltage ripple is about 3.4mV.

A high‐efficiency fast‐transient‐response V 2 ‐controlled boost converter with a small equivalent series resistance (ESR) capacitor is presented. The proposed boost converter can achieve a fast and stable load transient response without relying on the ESR of the output capacitor. The switching frequency of the proposed boost converter is 500 kHz for a nominal 2.5–4.2 V input and a 3.3–5 V output application. Experimental results show that the transient recovery time inheriting the advantage of V 2 control is shorter than 6.4 µs with the load step from 250 to 20 mA and the highest efficiency can be up to 95.4%. The proposed boost converter has been fabricated with a 0.35 µm 2P4M CMOS process, the total chip area is about 1.5 × 1.5 mm 2 , including the PADs.

This paper presents an adaptive constant on-time control scheme based on V2 constant on-time (V2 COT) architecture with current feedback. Due to the very small equivalent series resistance (ESR) of the output capacitor, stability issues may arise. In this paper, the ripple is obtained by applying two-stage filtering to extract the AC component of SW signal. The ripple is summed with the output signal to form the inner loop. Type-II compensated outer loop is incorporated to enhance output voltage accuracy while preserving the fast transient response characteristic of the ripple-based COT architecture. The designed converter delivers 3.3 V and 5 V outputs from an input range of 8–36 V, with a maximum output current of 35 A and a switching frequency of 510 kHz.

This paper proposes an online condition monitoring system for aluminum electrolytic capacitors used as dc-link capacitors in industrial power converters. Electrolytic capacitors are one of the most fragile components of a power converter system because of their wear-out failures and short lifespan. Therefore, the use of condition monitoring systems for aluminum electrolytic capacitors allow preventive maintenance to be performed, thereby avoiding unexpected shutdown and downtime. The dominant wear-out mechanisms in aluminum electrolytic capacitors are characterized by the increase in equivalent series resistance. Hence, the condition monitoring system proposed in this paper is based on the online estimation of the capacitor's equivalent series resistance using the switching frequency components of the dc-link capacitor voltage and current. The equivalent series resistance estimation method is tested using the PSpice circuit simulator and is validated experimentally using a custom-made inverter. Finally, the equivalent series resistance estimation method is adapted for the condition monitoring of capacitors in industrial power converters and the proposed condition monitoring system is implemented in a commercial ac drive system to prove the applicability of the proposed method to industrial power converters.