Ripple Compensation Based On COT Control Mode

Paolo Nora Paolo Nora, co-author of the paper “A novel sufficient condition to avoid sub-harmonic oscillations for Buck converters with constant on-time control” talks to us about their work page 305. I am part of the Architecture Definition Team of the Analogue Power and Interface Division (APID) of Microchip Technology Inc., and I collaborated with Profs. Bizzarri and Brambilla of the Politecnico di Milano on the topic of stable operation of Constant-ON-Time (COT) control, which is one of the most common control methods for analogue point-of-load (POL) Buck regulators. Indeed, my main area of interest is the architectural definition of analogue switch-mode regulators. A few years ago, I became aware of the topic of power integrity for my field of work. Both areas are very closely related, since POL regulators are often deployed in applications where power integrity considerations become increasingly critical for a successful power system design. The topic of Constant-ON-Time (COT) control, and – more generally – of ripple-based control of Buck converters has been a major focus for many power electronics researchers in the last few years, and different analysis methods have been used to determine its stability conditions. The importance of COT control (and its variations) of Buck POL converters is huge, due to the popularity of this control method in the industry. The reasons for such a wide popularity mainly stem from its superior load-transient performance over fixed-frequency architectures, and in the apparently simple design process it takes to develop the application. Simply put, the key design aspect is the phase relationship between the output voltage ripple fed to the controller and the Buck inductor current ripple. In addition, the total magnitude of the ripple seen by the controller plays an important role and must be adequate to ensure jitter-free operation. However, over many application cases encountered in practice, we've only seen a few of them being affected by confirmed instability issues (pulse-bursting operation) despite all recommended design practices being followed. This pushed us to consider different analysis methods to assess stability conditions, and here is where the nonlinear dynamical systems analysis expertise of profs. Bizzarri and Brambilla came to the fore. By using the state-variables methodology and state-plane graphical representations, and by leveraging nonlinear dynamical systems theory results, a new and more articulated sufficient condition for stable operation of the COT Buck converter was derived. This condition includes both circuit parameters and operating conditions. We have also shown that the well-known output capacitor time constant stability criterion is encompassed by the new sufficient condition. State-space analysis is a powerful method; however, its complexity rapidly explodes as the number of state variables increases. For the sake of manageability, the source of ripple fed to the COT control engine had to be limited to the resistor Re in series with the output capacitor, neglecting other well-known methods of ripple self-generation which would have added more state variables (i.e. more capacitors). The big question was then whether the simplified configuration would still be relevant from the practical perspective. Here is where some power integrity concepts, such as flat-impedance design of the POL stage and the power distribution network (PDN), played a key role. Indeed, resistor Re in series with the output capacitor may not just be a poorly controlled parasitic element – such as the equivalent series resistance (ESR) of an ordinary multi-layer ceramic capacitor (MLCC). In power-integrity-aware POL and PDN designs, the value of Re is intentionally controlled and – in some cases – it could even be implemented with a physical resistor. Also, if the POL stage is dedicated to some digital loads which are not particularly sensitive, the magnitude of the output voltage ripple generated by Re could also be adequate for a real-world application. We can conclude that the analysis of the simplified configuration presented in this Letter will become increasingly relevant as power integrity considerations will affect more and more POL/PDN designs. Another major challenge was experimental verification, whose description unfortunately exceeds the scope of the Letter. The state-variables method and the state-plane representation lend themselves very well to model rapid load transients and can predict the maximum load step that can be applied without saturating the COT control engine (i.e. engaging the minimum OFF time). This is also a new result and it is of utmost practical importance. Simply put, the outcome is that it should only take a very small load step to saturate the COT engine. If this does not happen, then it means that the design – for some reason – is not exploiting the full potential of COT control, and this should raise a red flag to the designer. As previously mentioned, this topic has attracted the attention of many researchers in power electronics over the last 10–15 years and there is a wealth of excellent, highly technical literature out there. I have to say that the perception of COT control is too simplistic for many practicing engineers: just make sure the controller is seeing enough voltage ripple, and that voltage ripple is in-phase with the inductor current ripple, and you're done! Unfortunately, experience reveals that the situation is not so simple. The challenge is how to convey all the highly technical results to a large community of users who simply do not have the time to dig into the fine details of POL design. The focus of many practicing engineers is not analogue design, not to mention POL design. Therefore, in the future, I see the highly technical analysis methods and results becoming available from the websites of many semiconductor vendors in the form of software tools as an extra aid for POL design verification, beyond the simple sets of equations provided by most datasheets. I also believe that the topic of digital implementation of COT-control and ripple-based control and their modeling will also grow exponentially.

Aluminum electrolytic capacitor (AEC) is one of the most age-affected components in ac–dc conversion, and its equivalent series resistance ( ESR ) is an important index for reflecting the healthy condition of AEC. In AEC-used boost power factor correction (PFC) converters, ESR of AEC causes a small jump in the switching ripple of output voltage at switching moments, especially at turn- off moments. This small jump is hardly observed at line-frequency scale, either using time-domain analysis or frequency-domain analysis. However using time–frequency analysis this jump is very prominent due to its singularity. In this article, an online ESR estimation method of AEC is proposed by using the wavelet transform (WT) based time–frequency analysis. The relationship between ESR and the jump amount of output voltage at turn- off moments is analyzed first, and then the ESR calculation model is derived using WT with the wavelet basis of the first derivative of Gaussian function. An appropriate sampling interval for the output voltage and the inductor current is determined. Besides, the online ESR estimation scheme is implemented including the hardware and software designs. Furthermore, a prototype of boost PFC converter with 220 V ac input and 360 V dc output is built, where an average current mode control chip UC3854 is used. Four factors are discussed for estimation accuracy in the experiment, and the estimated results are consistent with the results measured by LCR meter with a relative error less than 10%.

The discrete mapping model of current‐mode controlled buck converter with constant current load, taking account of composite output capacitors (parallel connection of two different types of capacitor branches, i.e. electrolytic capacitors and ceramic capacitors), is established. Based on the model, dynamical effects of varying output capacitance and equivalent series resistance (ESR) are investigated by bifurcation behaviours. The period of low‐frequency oscillation among coexisting fast‐slow scale instability is derived by exploring the loci of eigenvalues, while the operating regions are estimated. Time‐domain simulation and experimental waveforms are provided for verification of the theoretical analysis, indicating the existences of subharmonic oscillation and coexisting fast‐slow scale instability in the converter with variation of output capacitance and ESR. Research results reveal that the low‐frequency oscillation can be eventually eliminated due to a relatively large (or small) ESR and the capacitance in the same branch presents to identical tendency of dynamical effects on the converter. Moreover, the interaction effects between two parallel capacitor branches are demonstrated. It illustrates that the low‐frequency oscillation can be removed with smaller (or larger) ESR or capacitance in one branch of the composite output capacitors while larger (or smaller) ESR or capacitance in the other branch.

In this paper, a new constant on-time control with output capacitor equivalent series resistance (ESR) ripple compensation and offset cancellation for buck converter is presented. The proposed controller uses lossless capacitor current sensing circuit and an offset-cancellation circuit, which not only improves system stability, but also eliminates the output dc offset.

Multilayer ceramic capacitors (MLCC) have wide application in electronic due to its electrical characteristics: low equivalent series resistance (ESR) and high volume efficiency. One of the MLCC manufacturing problems is the choice of composition for the end pastes. The experimental results of the termination pastes composition influence on the quality high-voltage MLCC investigation are presented. The causes of the defects appearance in the termination are determined, the composition of the termination paste, which ensures the quality contact of the internal electrode with the external, is proposed.

This paper describes an automated test configuration that is used for rapid characterization of the equivalent series resistance (ESR) of ceramic multilayer capacitors. The primary components in this system are a coaxial resonant line, an HP 8753D vector network analyzer, and a personal computer. Sample measurements are provided for several 1206 style capacitors, and the trends in ESR versus the internal capacitor architecture are presented.

An in-depth analysis on the load transient operation of a buck converter with auxiliary current control is presented in this article. The analysis quantifies the effects of nonideal characteristics, such as the equivalent series resistance, inductor current and output voltage ripples, time delay, and slew rate of the load current, on the fluctuation of the output voltage in a practical implementation. The analysis results reveals that some of the non-idealities may cancel each other out and become negligible in the implementation. A design considering the nonidealities can achieve the transient-wise capacitor charge balance of the output capacitor and minimize the output voltage deviation during the load transient. The agreement between the simulation and experimental results validates the effectiveness and precision of the proposed analysis and design.

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One of the key parameters that affects efficiency, power density and performance of a supercapacitor (SC) is the equivalent series resistance (ESR). In this study we propose a method to estimate ESR from the charging kinetics which has practical applications. Therefore, to study the ESR of the SC we must look at the different factors that affect this resistance. In this study, the rise time extracted from the charging kinetics curves of the SC was used as an indirect method to investigate the ESR of the SC. Three different parameters were taken into account: ionic mobility, solvent material and pore cavity size of the porous electrode. The results offer enlightening information for optimizing the design of the SC with higher performance and smaller ESR values that will be translated into a better energy storage technologies.

This paper presents the equivalent series resistance (ESR) modeling method of filter components and its stability impact of LCL filtered grid-connected voltage-source converters (VSCs). First, the time-domain models of filter inductor and capacitor are developed for modeling the ESR effect, which are used in simulations. Then, the current control loop gains of the grid-connected three-phase VSC, which include the ideal LCL filter and the ESR-modeled LCL filter are compared. The result shows that the ESR affects both the resonance peak and the phase characteristic in the frequency domain. Finally, in order to verify accuracy of proposed model, the loop gain is measured by network analyzer in the experimental set up, which shows that the analytical loop gain with proposed ESR modeled inductor agrees very well with experimental value. This verification means that the ESR modeling method is useful for an accurate stability analysis.

Taking a buck converter in continuous conduction mode as an example, the improved digital average voltage (IDAV) control technique with capacitor current compensation is presented, and the operation principle and control law are analyzed in detail. The stability and transient performance impacted by the compensation coefficient are investigated by sampled-data modeling, and the optimal compensation coefficient for the fastest load transient performance is found. The analysis results show that the compensation coefficient can be regarded as a virtual equivalent series resistor (ESR) of the capacitor, which affects the stability and transient performance of the system without increasing output voltage ripple. Experimental results are given to verify the correctness of the theoretical analysis.

This paper develops a novel methodology for voltage regulation and equal current distribution of parallel-buck DC-DC converters. Such converters are modeled as linear averaged state-space system models with adjustable loads. Two measurements, such as output voltage and inductor current, are used to accomplish the design of an adaptive backstepping sliding mode controller for the parallel-buck DC-DC converters. Based on the singular perturbation method, a reduced order model is derived in order to show that the effect of equivalent series resistance (ESR) of the capacitor can be ignored and the parallel converters can be well approximated by the reduced order model. With the reduced order model, an adaptive sliding mode control utilizing backstepping approach is proposed to control the parallel-buck DC-DC converters. This proposed control method has been verified by computer simulations, and has also been proven capable of giving satisfactory voltage regulation performance under input voltage variations and load changes.

Summary form only given. In this work it is shown that the dielectric constant or the capacitance of commercial capacitors are dependent on the following parameters: the voltage applied, the charge and discharge of pulse repetition rate, temperature, and frequency. The study of these parameters is essential for applications of ceramic capacitors in high-energy storage systems and in nonlinear transmission lines (NLTLs) used for RF generation. To accomplish that two basic circuits are described for measuring the capacitance or ε: 1) on static conditions (i.e. by varying the charging DC voltage across C for checking the dielectric nonlinearity) and 2) on dynamic conditions (under pulse repetition rate or temperature variation) to determine the respective C variation. Finally, the ESR (equivalent series resistance) of the dielectric and its dissipation factor are also measured using an Agilent LCR bridge/ 30 MHz to verify the ceramic capacitor losses, a key issue for NLTL applications as the line attenuation constant increases with frequency.