Dynamically Reconfigurable Memory Address Mapping for General-Purpose Graphics Processing Unit

Recent advancements in 3D-stacked DRAM such as hybrid memory cube (HMC) and high-bandwidth memory (HBM) promise higher bandwidth and lower power consumption compared to traditional DDR-based DRAM. However, taking advantage of this additional bandwidth for improving the performance of real-world applications requires carefully laying out the data in memory which incurs significant programmer effort. To alleviate this programmer burden, we investigate application-specific address mapping to improve performance while minimizing manual effort. Our approach is guided by the following insights: (i) toggling activity of address bits can help determine strategies to improve parallelism within memory but this metric underestimates conflicts and (ii) modern memory controllers reorder address requests and therefore any toggling activity measured from an address trace is non-deterministic. Furthermore, our position is that analyzing individual address bits results in poor estimates for actual conflicts and exploited parallelism and that entropy needs to be calculated for groups of address bits. Therefore, we calculate window-based probabilistic entropy for groups of address bits to determine a near-optimal address mapping. We present simulation results for ten applications that show a performance improvement up to 25% over fixed address-mapping and up to 8% over previous application-specific address mapping for our proposed approach.

In the development process of multi-core processors, the Network on Chip optimizes the storage structure, but the problem of “storage wall” still exists. There are many ways to alleviate this problem. The improvement of memory access performance can be obtained for appropriate address mapping between cache levels. As far as the performance index of address mapping is concerned, it can be considered from the perspectives of memory access bandwidth and latency in different levels of the storage system. Therefore, a module-level detection tool is designed to test the memory access performance. Based on the hardware emulation acceleration platform, this tool solves the online/offline data collection of memory access bandwidth and latency. And it implements the functions for extremely long simulation times, which is data capture, analysis, and processing. Under different address mapping and data types of different application scenarios, This tool tests memory access performance between cache modules. Based on the data-affinity address cross-mapping method, this thesis proposes an address mapping optimization scheme that binds the directory controller unit and the local memory. Through the module-level memory access performance test, the optimized data affinity and low-order address cross-mapping method increases the memory access bandwidth by 8% and the maximum bandwidth by 9% when processing scheduling-intensive data. In a word, this thesis establishes the memory access performance analysis method which is “benchmark test program, module-level memory access performance detection, address mapping optimization and configuration”.

Reconfigurable architectures become popular in consumer applications as they require low Non-Recurring Engineering costs. Certain FPGA families provide the Dynamic Partial Reconfiguration (DPR) mechanism which allows to modify parts of a device on-the-fly. The high reliability constraints in automotive systems requires safe communications between ECUs (Electronic Control Unit). This paper presents a support for fault-tolerant communication modes among ECUs by the use of the dynamic reconfiguration paradigm. Also in this paper, a method of integrating dynamic reconfiguration in Autosar environment is presented.

Mission reliability evaluation of high‐performance unmanned aerial vehicle (UAV) swarms faces significant challenges because of their tightly coupled mission profiles, dynamic reconfiguration mechanisms, and heterogeneous node interactions. Traditional reliability models fail to capture these complexities, particularly the impact of mission reconstruction on the UAV swarm adaptability. To address this gap, we propose a novel mission reliability evaluation framework that integrates an effective mission loop analysis and dynamic network reconfiguration. First, we analyzed the system composition and interaction of high‐performance UAV swarms and designed a mission reliability evaluation model based on effective mission loops. Second, we developed a dynamic reconstruction algorithm to autonomously reconfigure the swarm topology in response to node/edge failures, ensuring sustained operational capability. Third, by integrating the reliability evaluation model with the reconstruction algorithm, we built a high‐performance UAV swarm mission reliability evaluation method that explicitly incorporates mission reconstruction. A case study of a 10‐UAV swarm strike mission validated the proposed framework. The results demonstrate its effectiveness in mission reliability evaluation of high‐performance UAV swarms, with potential extensions to heterogeneous aviation systems.

This article presents a description of the method of increasing the stability of data transmission in a software-defined network (SDN) by means of its dynamic reconfiguration, considering the parameters of the quality of service (QoS) of communication channels and the reliability of nodes. The existing algorithms do not provide a comprehensive solution to the problem of determining the most optimal path that would provide a connection from the source point to the destination. They consider only certain parameters of the network, depending on which the time spent on communication between nodes is less than in the case of other routes. In conditions of growth in the number of users of computer networks and the number of node switches, there is an urgent problem of increasing the stability of data transmission in branched computer networks. It is proposed to solve this by considering the quality of service parameters of communication channels when constructing routes. The aim of the research is to increase data transmission stability in a virtual software-defined network in conditions of failures of nodes and increasing loads on communication channels. The first objective of the research is to create a method for finding a set of non-intersecting optimal paths that would consider various metrics of the quality of service of communication channels. The second research objective is to develop a dynamic reconfiguration mechanism for SDN switch flow tables to be able to reroute traffic in the event of individual node failure. In the course of the research, the first objective was performed by mathematically substantiating the construction of the generalized weight matrix of transitions between the nodes of the network graph. When creating a request to determine a route for traffic in the network, its status and indicators are updated in order to increase the accuracy of data on available resources and establish the optimal path that meets the quality of service criteria. It is proposed to consider four quality of service metrics for path construction: the number of hops between vertices, the available bandwidth, the time delay, and the percentage of lost packets. Using the generalized transition weight matrix, the SDN controller selects the most optimal path among a set of alternative non-intersecting paths. Then, using the reliability coefficients of the nodes as a constraint to choose the optimal path between the vertices, the controller chooses the main route from the set of alternatives according to the requirement for the reliability of the nodes set by the administrator, and considers the other routes as backup. The second task was solved by proposing a method of dynamic network reconfiguration using known paths. If in the process of traffic transmission there is a failure in the intermediate links of the network or the communication channels between them, then monitoring data of the SDN controller are used for reconfiguration and bypassing the problem area, which allows the controller to quickly choose an alternative path for sending traffic and build a new path based on already known data about communication channels in the network. The obtained results of theoretical studies testify to the correctness of the chosen solutions and proposals for the objectives set in the article.

Upcoming reconfigurable Multiprocessor Systems-on-Chip (MPSoCs) present new challenges for the design and early estimation of technology requirements due to their runtime adaptive hardware architecture. The usage of simulators offers capabilities to overcome these issues. In this article, MPSoCSim, a SystemC simulator for Network-on-Chip (NoC) based MPSoCs is extended to support the simulation of reconfigurable MPSoCs. Processors, such as ARM and MicroBlaze, and peripheral models used within the virtual platform are provided by Imperas/OVP and attached to the NoC. Moreover, traffic generators are available to analyze the system. The virtual platform currently supports mesh topology with wormhole switching and several routing algorithms such as XY-, a minimal West-First algorithm, and an adaptive West-First algorithm. Amongst the impact of routing algorithms regarding performance, reconfiguration processes can be examined using the presented simulator. A mechanism for dynamic partial reconfiguration is implemented that is oriented towards the reconfiguration scheme on real FPGA platforms. It includes the simulation of the undefined behavior of the hardware region during reconfiguration and allows the adjustment of parameters. During runtime, dynamic partial reconfiguration interfaces are used to connect the Network-on-Chip infrastructure with reconfigurable regions. The configuration access ports can be modeled by the controller for the dynamic partial reconfiguration in form of an application programming interface. An additional SystemC component enables the readout of simulation time from within the application. For evaluation of the simulator timing and power consumption of the simulated hardware are estimated and compared with a real hardware implementation on a Xilinx Zynq FPGA. The comparison shows that the simulator improves the development of reconfigurable MPSoCs by early estimation of system requirements. The power estimations show a maximum deviation of 9mW at 1.9W total power consumption.

Large and complex decentralized systems with autonomous components often require appropriate mechanisms for cooperation, reliability, and dynamic reconfiguration. It is crucial that these mechanisms allow the system to execute continuously for a long period of time with minimal disruption, despite failure or reconfiguration of some components. They should also allow various components to interact in complex ways. We develop a uniform software architecture for implementing these mechanisms using generalized techniques and common functionalities. These mechanisms also support a variety of application-dependent policies. We present a manufacturing example that motivates our work.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

To utilize the full potential of modern chip multiprocessors and obtain scalable performance improvements, it is critical to mitigate resource contention created by multithreaded workloads. In this article, we describe ReSense, the first runtime system that uses application characteristics to dynamically map multithreaded applications from dynamic workloads—workloads where multithreaded applications arrive, execute, and terminate continuously in unpredictable ways. ReSense mitigates contention for the shared resources in the memory hierarchy by applying a novel thread-mapping algorithm that dynamically adjusts the mapping of threads from dynamic workloads using a precalculated sensitivity score. The sensitivity score quantifies an application's sensitivity to sharing a particular memory resource and is calculated by an efficient characterization process that involves running the multithreaded application by itself on the target platform. To measure ReSense's effectiveness, sensitivity scores were determined for 21 benchmarks from PARSEC-2.1 and NPB-OMP-3.3 for the shared resources in the memory hierarchy on four different platforms. Using three different-sized dynamic workloads composed of randomly selected two, four, and eight corunning benchmarks with randomly selected start times, ReSense was able to improve the average response time of the three workloads by up to 27.03%, 20.89%, and 29.34% and throughput by up to 19.97%, 46.56%, and 29.86%, respectively, over the native OS on real hardware. By estimating and comparing ReSense's effectiveness with the optimal thread mapping for two different workloads, we found that the maximum average difference with the experimentally determined optimal performance was 1.49% for average response time and 2.08% for throughput.

Current FTL schemes have inevitable limitations in terms of memory requirement, performance, garbage collection overhead, and scalability. To overcome these limitations, we propose a workload adaptive flash translation layer referred to as WAFTL. WAFTL explores either page-level or block-level address mapping for normal data block based on access patterns. Page Mapping Block (PMB) is used to store random data and handle large number of partial updates. Block Mapping Block (BMB) is utilized to store sequential data and lower overall mapping table. PMB or BMB is allocated on demand and the number of PMB or BMB eventually depends on workload. An efficient address mapping is designed to reduce overall mapping table and quickly conduct address translation. WAFTL explores a small part of flash space as Buffer Zone to log writes sequentially and migrate data into BMB or PMB based on threshold. Static and dynamic threshold setting are proposed to balance performance and mapping table size. WAFTL has been extensively evaluated under various enterprise workloads. Benchmark results conclusively demonstrate that proposed WAFTL is workload adaptive and achieves up to 80% performance improvement, 83% garbage collection overhead reduction and 50% mapping table reduction compared to existing FTL schemes.

Emerging trends in design of real-time digital signal processing systems indicate that in the future, a significant amount of performance improvement can be achieved using dynamically reconfigurable embedded architectures consisting of reconfigurable, general-purpose components. Although embedded real-time systems have long been prevailing in our society, no firm scientific base has been established yet to handle timing requirements in a systematic manner in real-time embedded computing. Because of this lack of the scientific base, many embedded systems have been designed in an ad hoc manner and most of them have been customized to specific applications, showing inflexibility for the other type of applications. This paper proposes a dynamically reconfigurable embedded architecture which bridges the gap between the embedded system and ASICs. This architecture combines a reconfigurable hardware processing unit with a software programmable processor. The main goal is to take advantage of the capabilities of both resources. While the processor takes care of all sequential computations the reconfigurable hardware takes specialized vector operations. With such integrated system architecture, specific properties of applications, such as parallelism, regularity of computation and data granularity can be exploited by creating custom operators, pipelines and interconnection pathways. To handle the conflicting requirements of being a flexible architecture and implement some application-specific algorithms, a dynamically reconfigurable embedded architecture is proposed. The proposed architecture consists of arithmetic operation-level configurable modules interconnected through multiple data buses that can be logically configured to form one or more pipelines before a specific application is initiated and remains unchanged till the completion of the application. This architecture is targeted at high throughput and real time signal processing applications. The idea of dynamic reconfiguration - changing a circuit while it is operating - is exploited. In particular, we illustrate how dynamic reconfiguration can achieve significant performance improvement.

Wireless sensor networks have attracted much research effort in the past five years. With TinyOS, there exists a widely used, microthreaded operating system targeted for single processor sensor nodes. It requires only minimal processing and memory resources. Many research activities in the wireless sensor area focus on the design of efficient protocols in the MAC and network layer. SDL - a high-abstraction level formal description language - has long been used for modeling, simulation, and verification of communication protocols. In this paper, we present a mapping approach and optimizations to derive efficient component-based event-driven TinyOS applications from SDL models. We show, how the basic SDL concepts are reflected in the TinyOS component architecture.

Embedded devices are equipped with specialized microcontrollers for each device. If an ultra-general purpose microcontroller with all peripherals existing, any kind of embedded device can be developed by such microcontroller. However, such microcontrollers cannot be built due to the scale and price. A dynamic partial reconfigurable microcontroller (DPR microcontroller), which has a function to switch circuits for each application, can realize an ultra-general purpose microcontroller that can be used for any application. For the realization and practical use of DPR microcontrollers, it is necessary to develop a hardware library-like structure in which optimized interface circuits for each peripheral device are designed in advance. In addition, the impact of dynamic switching of peripheral device interface circuits on performance has not been studied, so it is necessary to evaluate these effects. Using dynamic partial reconfiguration, we measure the execution time, circuit size of the entire system, and power performance improvement ratio of a single system that displays a binarized image on an LCD module after gray scaling and binarizing the image. The results show that the dynamic partial reconfiguration can be used to improve the performance of the system. As a result, we confirmed that the system works correctly even when dynamic partial reconfiguration is used. In addition, we were able to improve the processing speed by about 2.13 times compared with software processing, and reduce the circuit size by about 24%. We also achieved a 13.8-fold improvement in power consumption.

We have transported the code from Earth Simulator (ES) to K-Computer (KC) keeping a scalability. The base code achieved remarkable linear scalability and significant parallelization efficiency in EC before. The reason of success is that, taking into account the architectural differences between ES and KC, we improve the program step by step. Actually, the program showed a 37% improvement in the total performance with the implementations such as hybrid OpenMP and MPI parallelization, and the optimal rank mapping, and the MPI communication concealment, including removing the unnecessary processes such as zero clear and data copy.

Low-Density Parity-Check (LDPC) codes are a well known Error Correction Code family used for instance, in wireless and satellite communication links. Error correction performance of LDPC codes was further enhanced by extending it to higher order Galois fields, giving rise hence to the so-called non-binary LDPC codes (NB-LDPC). Error correction performance improvement (CCSDS 2014) is the main reason behind the adoption by the Consultative Committee for Space Data Systems (CCSDS) of the NB-LDPC codes in the experimental specification for the future next generation uplinks (CCSDS 2014, 2015). The high error correction efficiency for short frames make NB-LDPC codes a good candidate for IoT applications. However, the performance gain comes at the expense of a high decoding computational complexity (CCSDS 2014; Conde-Canencia et al. 2009). In this paper, an x86 multicore NB-LDPC decoder implementation is provided. This decoder that implements the FFT-SPA algorithm provides a throughput improvement of about 1.3 × to 2.7 ×, a latency reduction of more than 95% and a power consumption halved in comparison with the most efficient works on GPU (Graphics Processing Unit) device. Indeed, an efficient memory mapping and computation optimizations on the x86 architecture enable to achieve a higher decoding throughput than the GPU-based in similar experimental setup. Consequently, the throughput efficiency, the low processing latency associated with a low power consumption makes this proposed multicore implementation practical and attractive for real time implementations of NB-LDPC decoders in future SDR or Cloud-RAN systems for CCSDS standard and IoT applications.

This paper investigated an effective water evaporation optimization algorithm based approach to improve the effectiveness of the distribution network. The optimal accommodation of multiple photovoltaic (PVs) generation source and its coordination with network reconfiguration is used to minimize the network energy loss. The coordination of PVs and dynamic network reconfiguration of the distribution network is a complicated optimization problem. The problem of dynamic reconfiguration of the distribution network is mixed-integer, non-differentiable, and of an extremely complex combinatorial nature. Besides, the constraint of radiality usually rises the complexity of the evolutionary meta-heuristic optimization algorithms. The developed methodology is based on the foundation of graph theory, which limits the search space and also prevents repetitive mesh checks. The developed methodology is proficient and ensures that only possible radial topologies are generated. This coordinated operational planning is subjected to the distribution system constraints such as limits of feeder current, limits of node voltage, and power balance, etc. The suggested methodology is tested on the IEEE radial 33-bus distribution system. The results show that optimal accommodation of multiple PVs and its coordination with dynamic network reconfiguration reduces the network loss to 20.24% and also maintains node voltage within the specified limits.KeywordsPhotovoltaicNetwork reconfigurationDistribution networkWater evaporation algorithm