Simulating Reconfigurable Multiprocessor Systems-on-Chip with MPSoCSim

Reconfiguration technique has been considered as one of the most promising electronic design automation (EDA) technologies in MPSoC design paradigms. However, due to the unavoidable latency in the reconfiguration procedure, it still poses a significant challenge to efficiently analyze the trade-offs for the software/hardware execution, static reconfiguration and dynamic reconfiguration. In this paper we first present a heterogeneous MPSoC middleware to support state-of-the-art dynamic partial reconfigurable technologies. Furthermore, we evaluate the reconfiguration latency and analyze the trade-off for the dynamic partial reconfiguration technologies.

Application specific integrated circuits are used to provide real-time performance of handheld devices within the compact physical size and low energy dissipation. However, these circuits are inflexible for any modification like redesign and refabrication. Reconfigurable architectures are promising alternative for conventional computing devices such as application-specific integrated circuits. It provides high-level flexibility to adapt the applications through dynamic hardware customization even after fabrication. A reconfigurable computing system design considers the peculiarities of the targeted application domain along with architectural issues like dynamic reconfiguration, partial reconfiguration, hardware/software co-design and context management. A brief survey has been carried out to understand the concepts and applications of CGRA, FPGA, SoC, NoC, MPSoC, dynamic partial reconfiguration, hardware/software co-design, design-space exploration, multi-objective optimization, genetic algorithm and reconfigurable computing on wireless communications. This paper deals with the survey on modeling, design, implementation and evaluation of coarse-grained dynamically reconfigurable processor architectures targeting the real-time embedded computing domain.

A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using dynamic partial reconfiguration of an FPGA, all the modes can be implemented on the same reconfigurable region, requiring only an area that can contain the biggest mode. This can save considerable chip area. Conventional dynamic partial reconfiguration techniques generate a configuration for every mode separately. As a result, to switch between modes the complete reconfigurable region is rewritten, which often leads to long reconfiguration times. In this paper we give an overview of research we conducted to reduce this overhead of dynamic partial reconfiguration for multi-mode circuits. In this research we explored several joint optimization strategies at different stages of the tool flow.

Reconfigurable architectures become popular in consumer applications as they require low Non-Recurring Engineering costs. Certain FPGA families provide the Dynamic Partial Reconfiguration (DPR) mechanism which allows to modify parts of a device on-the-fly. The high reliability constraints in automotive systems requires safe communications between ECUs (Electronic Control Unit). This paper presents a support for fault-tolerant communication modes among ECUs by the use of the dynamic reconfiguration paradigm. Also in this paper, a method of integrating dynamic reconfiguration in Autosar environment is presented.

Debugging of Field-Programmable Gate Arrays (FPGAs) is a difficult task due to the limited access to the internal signals of the design. Embedded logic analyzers enhance the signal observability for FPGAs. These analyzers are implemented on the FPGA resources and they use the embedded memory blocks as trace buffers, so a limited number of signals can be observed using these analyzers due to resources constraints. Changing the traced set of signals requires re-synthesis, placement and routing of the whole design. In this paper, we propose a new methodology for FPGA debugging to change dynamically the set of signals to be observed at runtime, and consequently minimize the time required for debugging. The proposed methodology utilizes the Dynamic Partial Reconfiguration (DPR) technique to dynamically switch between different sets of signals. DPR creates a reconfigurable module (RM) to route each set of signals to an embedded logic analyzer. We demonstrate the proposed approach using Xilinx FPGA tools, finding that changing the set of signals to be observed requires only few milli-seconds to re-program the reconfigurable region (RR). The area overhead of the proposed methodology is lower than other traditional methods of using multiplexers as the DPR allows the routing module to only use buffers to connect a set of signals to the embedded logic analyzer.

The design and test of Multi-Processor System-on-Chip (MPSoCs) including software is one of the biggest challenges in today's system design. This applies in particular when short time-to-market constraints impose serious limitations on the exploration of the design space. The use of virtual platforms can help in decreasing the development cycles. In this paper, we present a cloud-based environment allowing the design of virtual platforms and prototyping of the system including complex software with prerecorded data or testbenches. Afterwards, the created design can also be synthesized for Xilinx FPGAs. Additionally, this paper presents the use of this remote virtual prototyping environment in a hardware-related programming laboratory with more than 350 participating undergraduate students. This large number of attendees leads to a lot of issues regarding the supervisory relationship as well as providing enough hardware resources in terms of boards. Nevertheless, we want to give the students hands-on experience when programming an embedded system on an FPGA-board. The cloud-based infrastructure allows us to respond to these difficulties by implementing a Software-in-the-Loop simulation based on an instruction set simulator. Doing so the students can design and implement their codes for the targeted architecture and prototype and debug it on a virtual platform. Since the course is mandatory we expect many students with limited experience about hardware-related programming. In this paper we show that especially these students will profit from the additional possibilities which are offered by a remotely available virtual prototyping platform.

Embedded devices are equipped with specialized microcontrollers for each device. If an ultra-general purpose microcontroller with all peripherals existing, any kind of embedded device can be developed by such microcontroller. However, such microcontrollers cannot be built due to the scale and price. A dynamic partial reconfigurable microcontroller (DPR microcontroller), which has a function to switch circuits for each application, can realize an ultra-general purpose microcontroller that can be used for any application. For the realization and practical use of DPR microcontrollers, it is necessary to develop a hardware library-like structure in which optimized interface circuits for each peripheral device are designed in advance. In addition, the impact of dynamic switching of peripheral device interface circuits on performance has not been studied, so it is necessary to evaluate these effects. Using dynamic partial reconfiguration, we measure the execution time, circuit size of the entire system, and power performance improvement ratio of a single system that displays a binarized image on an LCD module after gray scaling and binarizing the image. The results show that the dynamic partial reconfiguration can be used to improve the performance of the system. As a result, we confirmed that the system works correctly even when dynamic partial reconfiguration is used. In addition, we were able to improve the processing speed by about 2.13 times compared with software processing, and reduce the circuit size by about 24%. We also achieved a 13.8-fold improvement in power consumption.

Nowadays, the growing complexity in a wide variety of applications has led to the use of Multiprocessor Systems-on-Chip (MPSoCs). Networks-on-Chip (NoCs) have emerged as a scalable intra-chip communication technology for a high number of processing elements. However, the evolution of MPSoCs shows increasing communication requirements due to the growing number of PEs. This paper presents a novel Network-on-Chip microarchitecture that combines data transfers with data stream processing to exploit efficiently the transmission time. Data stream processing is enabled by a lightweight processing unit that is located within the transmission channels of the NoC. Thus, data can be processed by operations either in a processing element such as a MicroBlaze processor or inside the NoC while it is transferred. Operations executed by the NoC reduce the workload of the processing elements. In addition, the transmission time will be efficiently used. The novel microarchitecture is evaluated and compared to a state-of-the-art router on a Xilinx Zynq FPGA.

Multi-Processors System-on-Chip (MPSoCs) have emerged as the enabler technology for new computational paradigms such as Internet-of-Things (IoT) and Machine Learning. Network-on-Chip (NoC) communication paradigm has been adopted in several commercial MPSoCs as an effective solution for mitigating the communication bottleneck. The widespread deployment of such MPSoCs and their utilization in critical and sensitive applications, turns security a key requirement. However, the integration of security into MPSoCs is challenging. The growing complexity and high hyper-connectivity to external networks expose MPSoC to Malware infection and code injection attacks. Isolation of tasks to manage the ever-changing and strict mixed-criticality MPSoC operation is mandatory. Hardware-based firewalls are an effective protection technique to mitigate attacks to MPSoCs. However, the fast reconfiguration of these firewalls impose a huge performance degradation, prohibitive for critical applications. To this end, this paper proposes a lightweight broadcasting mechanism for firewall reconfiguration in NoC-based MPSoC. Our solution supports efficient and secure creation of dynamic security zones in the MPSoC through the communication management while avoiding deadlocks. Results show that our approach decreases the security reconfiguration process by a factor of 7.5 on average when compared to the state of the art approaches, while imposing negligible area overhead.

This paper presents a novel cell architecture for evolvable systolic arrays. HexCell is a tile-able processing element with a hexagonal shape that can be implemented and dynamically reconfigured on field-programmable gate arrays (FPGAs). The cell contains a functional unit, three input ports, and three output ports. It supports two concurrent configuration schemes: dynamic partial reconfiguration (DPR), where the functional unit is partially reconfigured at run time, and virtual reconfiguration circuit (VRC), where the cell output port bypasses one of the input data or selects the functional unit output. Hence, HexCell combines the merits of DPR and VRC including resource-awareness, reconfiguration speed and routing flexibility. In addition, the cell structure supports pipelining and data synchronization for achieving high throughput for data-intensive applications like image processing. A HexCell is represented by a binary string (chromosome) that encodes the cell's function and the output selections. Our developed evolvable HexCell array supports more inputs and outputs, a variety of possible datapaths, and has faster reconfiguration, compared to the state-of-the-art systolic array while maintaining the same resource utilization. Moreover, by using the same genetic algorithm on the two systolic arrays, results show that the HexCell array has higher throughput and can evolve faster than state-of-the-art array.

Recent research has shown that field programmable gate arrays (FPGAs) have a large potential for accelerating demanding applications, such as high performance digital signal process applications with low-volume market. The loss of generality in the architecture is one disadvantage of using FPGAs, however, the reconfigurability of FPGAs allow reprogramming for other applications. Therefore, a uniform FPGA-based architecture, an efficient programming model, and a simple mapping method are paramount for the wide acceptance of FPGA technology. This paper presents MASALA, a dynamically reconfigurable FPGA-based accelerator for parallel programs written in thread-intensive and explicit memory management (TEMM) programming models. Our system uses a TEMM programming model to parallelize demanding applications, including application decomposition into separate thread blocks and compute and data load/store decoupling. Hardware engines are included into MASALA using partial dynamic reconfiguration modules, each of which encapsulates a thread process engine that implements the hardware's thread functionality. A data dispatching scheme is also included in MASALA to enable the explicit communication of multiple memory hierarchies such as interhardware engines, host processors, and hardware engines. Finally, this paper illustrates a multi-FPGA prototype system of the presented architecture: MASALA-SX. A large synthetic aperture radar image formatting experiment shows that MASALA's architecture facilitates the construction of a TEMM program accelerator by providing greater performance and less power consumption than current CPU platforms, without sacrificing programmability, flexibility, and scalability.

Dynamic Partial Reconfiguration (DPR) allows the targeted FieldProgrammable Array (FPGA) to selectively update portions of the programmable logic while the remainder of the fabric stays active. Previously, designers were required to manually create DPR systems with minimal support from Computer Aided Design (CAD) tools. Xilinx ® ’s PlanAhead TM software now automates much of the DPR system generation process for ISE-based DPR systems. This paper presents EuTOPIA (EDK TO PlanAhead Implementation Automation), a CAD tool that extends the automation in Xilinx’s current DPR design flow to include microprocessor based designs. Given an architecture described in Xilinx’s Embedded Design Kit (EDK), EuTOPIA automates the process of converting it into a PlanAhead project for a DPR design. EuTOPIA abstracts the low level details of DPR implementation so that designers need only have nominal knowledge of the underlying process to create their initial DPR system. EuTOPIA is shown to reduce implementation time by a factor of 18 times over manual implementations by experienced designers, and can be further increased for novice designers. Over the design-cycle of a product where designers may generate tens or even hundreds of different implementations of their DPR design, these time savings could be extremely significant.

In the domain of Cyber-Physical Systems, the FPGA Dynamic Partial Reconfiguration (DPR) feature has been proved to be efficient to adapt the system hardware configuration to environment changes, also in the case of hard real-time constraints. Often, in this context, a single task can request multiple DPR to modify the platform configuration.However, also if in the hard real-time literature several works exploit the DPR process, to the best of our knowledge, no one deals with its scalability (i.e., the efficient management of multiple DPR requests).Hence, in this work, focusing on hard real-time systems, we conduct both a theoretical and practical investigation about the DPR scalability, discussing the obtained outcomes and the objectives to be achieved in the near future.

Various reconfigurable computing strategies are examined regarding their suitability for implementing shape-adaptive video processing algorithms of typical object-oriented multimedia applications. The utilisation of reconfigurability at different levels is investigated and the implications of designing reconfigurable shape-adaptive video processing circuits are addressed. Simple models for representing arbitrarily shaped objects and for mapping them into object-specific hardware designs are developed. Based on these models, several design and reconfiguration strategies, targeting an efficient mapping of shape-adaptive video processing tasks to a given reconfigurable computing architecture, are investigated. A number of real applications are analysed to study the trade-offs between these strategies. These include a shape-adaptive discrete cosine transform characterised by a limited number of different data-dependent computations and a shape-adaptive template matching method consisting of a virtually unlimited number of different computation possibilities. It is argued that shape-adaptive video processing algorithms with a relatively small number of different configuration contexts can often be more efficiently implemented as a static or multiconfiguration design, while a design employing dynamic or partial reconfiguration will be more suitable or even necessary if the number of different computation possibilities is relatively large.

FPGAs achieve smaller geometries and their reliability is becoming a severe issue. Non-functional properties, as Negative Bias Temperature Instability, affect the device functionality. In this work a novel methodology to address this issue is described, exploiting FPGAs flexibility. Dynamic Partial Reconfiguration is used to minimize aging impact on FPGAs' configuration memory.