Effect of III–V on insulator structure on quantum well intermixing

A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given "critical" dose. Above this dose, we still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic conduction is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies.

Selective modification of the band gaps of GaInNas/GaAs structures by quantum well intermixing techniques

Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

Monolithic active pixel detectors fabricated in SOI (silicon on insulator) technology are novel sensors of ionizing radiation which exploit SOI substrates for the integration of readout electronics with a pixel detector. The fully-depleted sensing diode is manufactured under the SOI buried oxide (BOX) in the volume of the `handle wafer', while readout circuitry occupies the upper silicon SOI `device layer'. However, the initial prototypes suffered from significant leakage currents and early breakdown of pixel diodes. These effects limited the production yield. Moreover, the p-wells within the device layer extended to the interface with the BOX, which caused some local potential wells below the BOX at the top of the depleted sensor area. As a result, the effective charge collection efficiency was significantly decreased. This paper describes a solution for these problems employing a thicker 4 ¿m SOI device layer. The use of this detector structure has increased the effective charge collection efficiency to over 99%.

With the rapid development of high-speed fiber communication, data center interconnections, and optical computing, photonic integrated chips have become essential for optimizing system performance and energy efficiency. While techniques like heterogeneous and hybrid integration face challenges in yield and cost, monolithic integration offers a simpler, more reliable solution. It enables the integration of active photonic devices and low loss passive waveguides without requiring coupling alignment. Quantum well intermixing (QWI) for photonic devices on InP substrates is particularly advantageous, eliminating secondary epitaxy and coupling losses. This paper investigates QWI applied to InGaAlAs/InGaAlAs MQWs, focusing on achieving significant photoluminescence (PL) wavelength blue shifts while maintaining film integrity. Additionally, the impact of QWI on the internal quantum efficiency and internal loss of FP lasers are explored.

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.

The influence of nitrogen implantation on the properties of silicon-on-insulator buried oxide using separation by oxygen implantation was studied. Nitrogen ions were implanted into the buried oxide layer with a high-dose of 1016 cm-2. The experimental results showed that the positive charge density of the nitrogen-implanted buried oxide was obviously increased, compared with the control sampes without nitrogen implantation. It was also found that the post-implantation annealing caused an additional increase of the positive charge density in the nitrogen implanted samples. However, annealing time displayed a small effect on the positive charge density of the nitrogen implanted buried oxide, compared with the significant increase induced by nitrogen implantation. Moreover, the capacitance-voltage results showed that the positive charge density of the unannealed sample with nitrogen implanted is approximately equal to that of the sample annealed at 1100 ℃ for 2.5 h in N2 ambient, despite an additional increase brought with annealing, and the buried oxide of the sample after 0.5 h annealing has a maximum value of positive charge density. According to the simulating results, the nitrogen implantation resulted in a heavy damage to the buried oxide, a lot of silicon and oxygen vacancies were introduced in the buried oxide during implantation. However, the Fourier transform infrared spectroscopy of the samples indicates that implantation induced defects can be basically eliminated after an annealing at 1100 ℃ for 0.5 h. The increase of the positive charge density of the nitrogen implanted buried oxide is ascribed to the accumulation of implanted nitrogen near the interface of buried oxide and silicon, which caused the break of weak Si-Si bonds and the production of positive silicon ions in the silicon-rich region of the buried oxide near the interface, and this conclusion is supported by the results of secondary ion mass spectrometry.

We investigate the influence of quantum-well intermixing (QWI) on the electronic band structure of GaInNAs∕GaAs multiquantum wells. The band structures and optical transitions have been calculated based on the band-anticrossing (BAC) model and Fick’s interdiffusion law for both intermixed and nonintermixed samples, respectively. The calculated results are consistent with the true optical transitions observed by photoluminescence excitation spectroscopy and secondary ion mass spectroscopy. Our investigation indicates that BAC model is valid for interdiffused quantum wells and verifies that the QWI process in GaInNAs∕GaAs multiquantum wells is induced mainly by the interdiffusion of In–Ga between the quantum wells and barriers.

In our previous work on silicon-on-insulator (SOI) photodetectors, we have used the deep-depletion effect in SOI substrates to construct the photoelectron in-situ sensing device (PISD). The PISD is a one-transistor active pixel sensor (1T-Aps) that is more compact than conventional CMOS sensors. In this work, we study the crosstalk between different pixels in the PISD, which is severe in a conventional SOI substrate. Through TCAD simulations, the use of a double SOI (DSOI) substrate is shown to suppress crosstalk between PISD pixels. The on extra buried oxide layer completely separates the substrate into two parts which shield the movements of charges across the adjacent cells. The impact of top Si thickness and buried oxide thickness is observed.

Cross-talk suppression in SOI substrates

The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.

In this work, a threshold voltage model of Tri-Gate Schottky-Barrier (TGSB) MOSFET is presented by coupling threshold voltage models of symmetric and asymmetric double-gate Schottky-Barrier (SB) MOSFET structures giving due weight to each structure. The electrostatic potentials of double-gate SB MOSFETs are obtained using evanescent mode analysis method considering light doping in the channel region. In TGSB MOSFETs, the leakiest path in the subthreshold regime of device operation is located at the mid of the bottom of the channel region. The minimum potential of this leakiest path is considered to be the virtual cathode potential, which is subsequently used to calculate the threshold voltage of the SB MOS devices. The effects of device parameters like oxide thickness, buried oxide (BOX) thickness, channel height, width, and length, doping concentration and Schottky-Barrier height on threshold voltage have been extensively studied in this work. The proposed model results have been verified with numerical simulation results obtained from the 3-D device simulator of Sentaurus TCAD.

TOPO- and pyridine-capped cubic CdSe quantum dots were prepared, and the effect of surface ligand exchange on the photoluminescence (PL) peak shift was investigated. From the analysis of PL spectra and TEM images, it was found that the decrease in diameter in the CdSe quantum dot and redistribution of its surface electronic density play different roles in the PL peak shift. The reduction in size of CdSe by ligand exchange caused a blue shift of the PL peak due to the quantum confinement effect, whereas the redistribution of surface electronic density of CdSe by the exchange of TOPO with pyridine resulted in a red shift of 23 meV on the average for the samples investigated. The result was also supported by the XPS characterizations.

The impact of changing the buried oxide thickness and the ground plane resistivity on the substrate cross-talk in ground plane silicon-on-insulator (GPSOI) cross-talk suppression technology is investigated. It is found that crosstalk increases with increasing oxide thickness for low resistivity ground planes but decreases with increasing oxide thickness for higher ground plane resistivities over certain frequency ranges. An optimum buried oxide thickness is identified.

High-quality InGaAsP/InP multi-quantum wells (MQWs) on the isolated areas of indium phosphide on silicon necessary for realizing a monolithically integrated silicon laser is achieved. Indium phosphide layer on silicon, the pre-requisite for the growth of quantum wells is achieved via nano-epitaxial lateral overgrowth (NELOG) technique from a defective seed indium phosphide layer on silicon. This technique makes use of epitaxial lateral overgrowth (ELOG) from closely spaced (1 µm) e-beam lithography-patterned nano-sized openings (∼300 nm) by low-pressure hydride vapor phase epitaxy. A silicon dioxide mask with carefully designed opening patterns and thickness with respect to the opening width is used to block the defects propagating from the indium phosphide seed layer by the so-called necking effect. Growth conditions are optimized to obtain smooth surface morphology even after coalescence of laterally grown indium phosphide from adjacent openings. Surface morphology and optical properties of the NELOG indium phosphide layer are studied using atomic force microscopy, cathodoluminescence and room temperature µ-photoluminescence (µ-PL) measurements. Metal organic vapor phase epitaxial growth of InGaAsP/InP MQWs on the NELOG indium phosphide is conducted. The mask patterns to avoid loading effect that can cause excessive well/barrier thickness and composition change with respect to the targeted values is optimized. Cross-sectional transmission electron microscope studies show that the coalesced NELOG InP on Si is defect-free. PL measurement results indicate the good material quality of the grown MQWs. Microdisk (MD) cavities are fabricated from the MQWs on ELOG layer. PL spectra reveal the existence of resonant modes arising out of these MD cavities. A mode solver using finite difference method indicates the pertinent steps that should be adopted to realize lasing.