Development of a Monolithic Active Pixel Sensor Using SOI Technology With a Thick Device Layer

Novel CMOS monolithic pixel detectors designed at KEK and fabricated at Lapis Semiconductor in 0.2 μm Silicon-on-Insulator (SOI) technology are presented. A thin layer of silicon oxide separates high and low resistivity silicon layers, allowing for optimization of design of detector and readout parts. Shallow wells buried under the oxide in the detector part screen the entire pixel electronics from electrical field applied to the detector. Several integration type SOI pixel detectors have been developed with pixel sizes 8–20 μm. The general features of 14 × 14 μm2 detectors designed on different wafers (CZ-n, FZ-n and FZ-p) were measured and compared. The detector performance was studied under irradiation with visible and infra-red laser, and also X-ray ionizing source. Using X-rays from an Am-241 source the noise of readout electronics was measured at different working conditions, showing the ENC in the range of 88–120 e−. The pixel current was calculated from average DC pedestal shift while varying the pixel integration time. The operation of the detector was studied under partial and full depletion conditions. The effects of temperature and detector bias voltage on noise and leakage current were studied. Characteristics of an ADC integrated in the front-end chip are also presented.

Cross-talk suppression in SOI substrates

Uncooled thermal detectors for infrared (IR) sensing have attracted attention for both military and civil applications. One of the evaluation parameters for a high performance bolometer is thermal coefficient resistance (TCR). During the last decade monocrystalline SiGe is presented as a new generation of low cost thermistor materials. [1] Although the SiGe thermistor materials, based on multilayer quantum well (MQW) structures, have been investigated for a few years, so far none of the reports have been able to evaluate TCR values rapidly due to the complicated process and compatibility with available tools. In this paper, we report a relatively facile microfabrication process of self-doping SiGe/Si MQW thermoelectrical arrays as well as their thermoelectrical properties.A 4-inch SOI wafer was used as the handle wafer for the growth of SiGe/Si MQWs. The thickness of silicon handle wafer part silicon on insulator (SOI) wafer is 500 μm with 1.5 μm BOX layer (SiO2). The total 5 periodic thickness of SiGe/Si MQW is 725 nm and grown on the SOI wafer, and then sputtered with 20 nm Ti layer and 70 nm Al layer sequentially. Then a second patterned metallized wafer was electroplated with Au interconnect lines and pads as electrical measurement leads. The two wafers were then bonded together face to face using a wafer-level adhesive wafer bonding [2]. After the bonding, the 500 μm thick Si layer of SOI wafer was removed by inductively coupled plasma (ICP) Etching etching. The ICP stops at the SiO2 layer, and the SiO2 is removed by using regular BOE (buffer oxide etches). The SiGe/Si film was then patterned by lithography and dry etching. With the electroplated Au electrode column connecting the film and the Au pads on target wafer, the thin film was then covered by the 50nm Ti by sputter and the 350nm SiN layer deposited by PECVD for enhancing infrared light absorption. Finally, the whole device layer was patterned by lithography and dry etching, during which the bonding polymer was completely removed by O2 plasma. The released arrays are shown in fig.1. Then, the dependence of current-resistance and the temperature-resistance are examined by the facile metallized leads and the results are shown in fig.2. The TCR (temperature coefficient of resistance) of the arrays is about -2.6%K-1 at 303K. This value is consistent with that of previous reported results [3]. In summary, a relatively facile microfabrication process has been developed for characterizing the thermoelectrical properties of SiGe/Si MQWs materials. The processed thermalelectrical arrays show an expected TCR value as mathematical simulation.

A 250 V thin-layer SOI technology based on a 1.5-μm-thick SOI layer is developed for high-voltage (HV) switching IC. HV thin-layer silicon on insulator (SOI) field p-channel LDMOS (pLDMOS) with thick gate oxide layer, SOI RESURF n-channel LDMOS (nLDMOS) with thin gate oxide layer, and low-voltage CMOS are monolithically integrated. Compared with the conventional SOI technology integrating field pLDMOS, the thickness of SOI layer is reduced from above 5 μm to only 1.5 μm. The field implant (FI) technology is adopted to eliminate channel discontinuity underneath the bird's beak and achieve shallow junction depth to avoid back gate (BG) punchthrough breakdown for the field pLDMOS. A BG punchthrough model is presented with simulation results. The field pLDMOS with breakdown voltage (BV) of -329 V and RESURF nLDMOS with BV of 338 V are experimentally realized. A 250 V switching IC using the field pLDMOS and RESURF nLDMOS as the level-shift and the output stage is also presented based on the developed thin-layer SOI technology.

In this paper, the noise properties of transistors on 90 nm silicon on insulator (SOI) and bulk CMOS technologies are investigated. At 20 GHz, the SOI and bulk devices have minimum noise figures of 1 dB and 2.3 dB, respectively, demonstrating the superior performance of the SOI technology. The corresponding maximum available gain is 13 dB and 12 dB, respectively. For the first time, the drain and gate noise coefficients of shortchannel SOI devices are extracted yielding values of 2.15 and 1.7, respectively. Theoretical aspects are discussed to identify the main noise sources and to gain insights for optimizations. Furthermore, examples of analog monolithic integrated circuits fabricated on SOI technology are presented. Measured results are a noise figure of 4 dB for a low noise amplifier (LNA) at 40 GHz, a single side band noise figure of 9 dB for a passive mixer at 40 GHz and a phase noise of -90 dBc at 1 MHz offset for an voltage controlled oscillator (VCO) at 60 GHz. To the knowledge of the authors, these are the best noise performances achieved to date for CMOS based transistors and circuits at millimeter wave frequencies.

By utilizing a lumped-multilayer-based method, we have studied the thermal behavior of a generalized rectangular macro with an extremely high power density of 2500 W/cm/sup 2/ on a microprocessor chip of average power density 40 W/cm/sup 2/. We consider both conventional bulk Si CMOS technology and silicon on insulator (SOI) CMOS. Practical features, including the presence of realistic packaging and interconnect structures are thoroughly analyzed. We found that the worst case temperature rise for such a hotspot is about 11% (/spl sim/7/spl deg/C) above the global chip temperature rise (/spl sim/80/spl deg/C) for 2500 W/cm/sup 2/ power density in SOI technology. As a result of the presence of buried oxide, the thermal behavior of a 15/spl times/300 /spl mu/m/sup 2/ macro in bulk technology is significantly different from SOI technology. It is also found that the existence of the interconnect layers and a solder ball optimally positioned right above the heated macro enables the heat flow to spread horizontally above the macro before eventually being dissipated downwardly toward the heat sink, thus decreasing the peak temperature rise of the macro in the device plane.

Characterization of SOI monolithic detector system

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness most be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices.

Vertical n-p-n bipolar transistors have been fabricated in silicon-on-insulator (SOI) films prepared by buried oxide implantation. Electrical device characteristics are shown to be comparable to those obtained on devices fabricated in bulk silicon, indicating no significant degradation owing to the buried oxide layer. Dielectric isolation in excess of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> Ω.cm and µ 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> V/cm is measured.

The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.

To achieve the monolithic active/passive integration on the III–V CMOS photonics platform, quantum well intermixing (QWI) on III–V on insulator (III–V-OI) is studied for fabricating multi-bandgap III–V-OI wafers. By optimizing the QWI condition for a 250-nm-thick III–V layer, which contains a five-layer InGaAsP-based multi-quantum well (MQW) with 80-nm-thick indium phosphide (InP) cladding layers, we have successfully achieved a photoluminescence (PL) peak shift of over 100 nm on the III–V-OI wafer. We have also found that the progress of QWI on the III–V-OI wafer is slower than that on the InP bulk wafer regardless of the buried oxide (BOX) thickness, bonding interface materials, and handle wafers. We have also found that the progress of QWI on the III–V-OI wafer is slower than that on the InP bulk wafer regardless of the buried oxide (BOX) thickness, bonding interface materials, and bulk support wafers on which the III–V-OI structure is formed (handle wafers). By comparing between the measured PL shift and simulated diffusions of phosphorus vacancies and interstitials during QWI, we have found that the slow QWI progress in the III–V-OI wafer is probably attributed to the enhanced recombination of vacancies and interstitials by the diffusion blocking of vacancies and interstitials at the BOX interface.

Cracks patterned lithographically into the buried oxide (BOX) layer of silicon-on-insulator wafers were found to substantially improve yield in the release of ultrasoft silicon cantilevers. The BOX layer is useful as an etch stop and sacrificial layer in microfabrication. However, compressive stress in the BOX membrane can cause it to buckle and crack when released. These cracks can damage delicate structures in the device layer and reduce yield. Cracks were patterned into the BOX layer prior to avoid critical regions near or under devices; these patterned cracks reduced damage to devices from spontaneous cracks in the BOX layer and improved yield.

Internal oxidation (ITOX) of the buried oxide (BOX) of low dose SIMOX wafers has attracted a lot of attention in the last few years for its beneficial effect on the electrical and structural properties of the BOX. Models have been proposed to explain the ITOX process in terms of atomic oxygen diffusing through the silicon device layer to the BOX where it reacts with the bottom silicon interface to produce new silicon dioxide. Using the models with fitted parameters has shown good agreement with experimental data. However, the details regarding the dissociation of oxygen molecules before entering the device layer as well as the reaction of atomic oxygen with the back device layer surface were left unattended. The results presented suggest that these two processes could have a significant impact on the oxidation results and thus need to be studied to arrive at a valid model for the ITOX process.

The sensitivity to heavy ions of nonhardened 0.25-/spl mu/m partially depleted (PD) silicon on insulator (SOI) and bulk technologies is studied with experiments, device, and circuit simulations. Comparable threshold linear energy transfer (LET) are found for both technologies. Nevertheless, SOI saturated cross section is much lower than bulk one. For nonhardened technologies, SOI is then less sensitive than bulk to heavy ions.

This paper describes the fabrication and the performance analysis of 65 nm PMOS using Silicon‐on‐Insulator (SOI) technology. As the technology evolved towards minimizing the scaling size, the scaling activity has it own limitations. The Silicon‐on‐Insulator (SOI) is the primary method used to overcome the scaling limitation. In this paper, the 65 nm PMOS device with 0.4 μm thickness of Silicon‐on‐Insulator (SOI) Technology was fabricated and the performance of the devices was analyzed by focusing on the electrical characteristics of Id‐Vd and Id‐Vg curves for bulk PMOS and the one with SOI technology. The fabrication process simulation and electrical characteristic was simulated using SILVACO TCAD ATHENA and ATLAS simulator. A very promising results were obtained, the device with SOI technology shows improvement in drain saturation current of Idsat = −269 uA/um from −257 uA/um of bulk PMOS (with increment of 4.7%) and the SOI device exhibits lower threshold voltage of pVth(SOI) = −0.2165 V compared to pVt...