Electrical Analysis of 65 nm PMOS Based on SOI Technology

This technical paper investigates the electrical analysis in sub 90 nm of PMOS. The investigation was carried out by using two different methods which is PMOS with strained silicon and Silicon‐on‐Insulator (SOI) technology. Strained silicon engineering has become a key innovation to enhance device on current. Recently, SOI technology has been widely accepted for use in mainstream high performance logic applications due to some advantageous offered over the bulk silicon. The performance of the devices is analyzed by focusing on the electrical characteristics of Id−Vd and Id−Vg curves for three different structures. Firstly, PMOS with strained silicon of Si3N4 capping layer covering the gate area and secondly the device with and without SOI technology. The fabrication process simulation was simulated by using SILVACO TCAD ATHENA simulator and the electrical characteristic was simulated by SILVACO TCAD ATLAS simulator to obtain Id−Vd and Id−Vg curves. A fruitful and knowledgeable results were reported from this paper, it could be seen that high tensile strain introduced to the device causing the drain current to decreased from Id(bulk) = −400 uA/um of bulk to Id(Strain) = −310 uA/um which is about 25% of decrement. Since the drain current decreased, the carrier mobility and the performance also decreased proportional to drain current. However when SOI technology is applied to the PMOS device, the drain current was increased up to Id(SOI) = −431 uA/um over the bulk, the increment of about 9.25% reported. A higher Id−Vg curve and lower threshold of about pVth(SOI) = −0.2178 V also reported from this paper which tells that the device with SOI technology exhibits low power consumption device and fast switching which in turns contribute to a faster performance.

In this paper, the noise properties of transistors on 90 nm silicon on insulator (SOI) and bulk CMOS technologies are investigated. At 20 GHz, the SOI and bulk devices have minimum noise figures of 1 dB and 2.3 dB, respectively, demonstrating the superior performance of the SOI technology. The corresponding maximum available gain is 13 dB and 12 dB, respectively. For the first time, the drain and gate noise coefficients of shortchannel SOI devices are extracted yielding values of 2.15 and 1.7, respectively. Theoretical aspects are discussed to identify the main noise sources and to gain insights for optimizations. Furthermore, examples of analog monolithic integrated circuits fabricated on SOI technology are presented. Measured results are a noise figure of 4 dB for a low noise amplifier (LNA) at 40 GHz, a single side band noise figure of 9 dB for a passive mixer at 40 GHz and a phase noise of -90 dBc at 1 MHz offset for an voltage controlled oscillator (VCO) at 60 GHz. To the knowledge of the authors, these are the best noise performances achieved to date for CMOS based transistors and circuits at millimeter wave frequencies.

A 250 V thin-layer SOI technology based on a 1.5-μm-thick SOI layer is developed for high-voltage (HV) switching IC. HV thin-layer silicon on insulator (SOI) field p-channel LDMOS (pLDMOS) with thick gate oxide layer, SOI RESURF n-channel LDMOS (nLDMOS) with thin gate oxide layer, and low-voltage CMOS are monolithically integrated. Compared with the conventional SOI technology integrating field pLDMOS, the thickness of SOI layer is reduced from above 5 μm to only 1.5 μm. The field implant (FI) technology is adopted to eliminate channel discontinuity underneath the bird's beak and achieve shallow junction depth to avoid back gate (BG) punchthrough breakdown for the field pLDMOS. A BG punchthrough model is presented with simulation results. The field pLDMOS with breakdown voltage (BV) of -329 V and RESURF nLDMOS with BV of 338 V are experimentally realized. A 250 V switching IC using the field pLDMOS and RESURF nLDMOS as the level-shift and the output stage is also presented based on the developed thin-layer SOI technology.

By utilizing a lumped-multilayer-based method, we have studied the thermal behavior of a generalized rectangular macro with an extremely high power density of 2500 W/cm/sup 2/ on a microprocessor chip of average power density 40 W/cm/sup 2/. We consider both conventional bulk Si CMOS technology and silicon on insulator (SOI) CMOS. Practical features, including the presence of realistic packaging and interconnect structures are thoroughly analyzed. We found that the worst case temperature rise for such a hotspot is about 11% (/spl sim/7/spl deg/C) above the global chip temperature rise (/spl sim/80/spl deg/C) for 2500 W/cm/sup 2/ power density in SOI technology. As a result of the presence of buried oxide, the thermal behavior of a 15/spl times/300 /spl mu/m/sup 2/ macro in bulk technology is significantly different from SOI technology. It is also found that the existence of the interconnect layers and a solder ball optimally positioned right above the heated macro enables the heat flow to spread horizontally above the macro before eventually being dissipated downwardly toward the heat sink, thus decreasing the peak temperature rise of the macro in the device plane.

The sensitivity to heavy ions of nonhardened 0.25-/spl mu/m partially depleted (PD) silicon on insulator (SOI) and bulk technologies is studied with experiments, device, and circuit simulations. Comparable threshold linear energy transfer (LET) are found for both technologies. Nevertheless, SOI saturated cross section is much lower than bulk one. For nonhardened technologies, SOI is then less sensitive than bulk to heavy ions.

Monolithic active pixel detectors fabricated in SOI (silicon on insulator) technology are novel sensors of ionizing radiation which exploit SOI substrates for the integration of readout electronics with a pixel detector. The fully-depleted sensing diode is manufactured under the SOI buried oxide (BOX) in the volume of the `handle wafer', while readout circuitry occupies the upper silicon SOI `device layer'. However, the initial prototypes suffered from significant leakage currents and early breakdown of pixel diodes. These effects limited the production yield. Moreover, the p-wells within the device layer extended to the interface with the BOX, which caused some local potential wells below the BOX at the top of the depleted sensor area. As a result, the effective charge collection efficiency was significantly decreased. This paper describes a solution for these problems employing a thicker 4 ¿m SOI device layer. The use of this detector structure has increased the effective charge collection efficiency to over 99%.

Novel SOI (Silicon On Insulator) model parameter extraction methodology based on the concept of SHE (Self-Heating Effect) free device modeling, is proposed and demonstrated for a 0.18 /spl mu/m PD (Partially Depleted) SOI technology. In this methodology, prior to SPICE parameter extraction, the device thermal resistances are measured and the current loss due to SHE is added back analytically to DC I-V data. Therefore, the parameters are free from SHE. DC, AC, and transient simulation results using this technology show good agreement with measurement data.

Characterization of SOI monolithic detector system

In silicon-on-insulator (SOI) technology, devices are dielectrically insulated from one another—usually by silicon dioxide. Unlike in conventional silicon devices, there is no direct contact between a transistor and the silicon substrate. The advantages of this type of isolation are many: reduced parasitic capacitances and reduced crosstalk between devices, improved current drive, subthreshold characteristics, and current gain. Silicon-on-insulator devices have been and are being used in several niche-market applications such as hightemperature and radiation-hard integrated circuits. However most importantly, SOI technology seems perfectly adapted to the needs of low-voltage, low-power (LVLP) electronic circuits. Because of the growing market for portable systems, LVLP technology is bound to soon become one of the drivers of the microelectronics industry, and SOI is likely to be part of it. Moreover major companies such as IBM, Sharp, Motorola, and Peregrine have announced upcoming lowpower and high-frequency lines of SOI products. The goal of this article is to introduce the reader to the basics of SOI device physics and the integrated-circuit applications of SOI.

Analysis of the breakdown voltage in SOI and SOS technologies

The relationship between that of silicon-on-insulator (SOI) technology and ordinary CMOS is presented followed with an examination of the basic features of MOSFETs fabricated under the SOI process. Such features include the intrinsic junction diodes, diffusion capacitance, floating-body effect, internal parasitic bipolar effects, the insulation layer and its consequences, and the self-heating effect. In addition to the fact that many of these features provide improvements in transistor design and performance over standard CMOS, SOI technology is poised to become competitive for small power supply applications.

A smart power transistor for high voltage inverter applications

– The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method. I.

As microprocessors enter the highly multi-core/multi-threaded era, higher density, lower latency embedded memory will be required to meet cache design needs. This paper describes a 500 MHz random cycle silicon on insulator (SOI) embedded DRAM macro which features a three-transistor micro sense amplifier, realizing significant performance gains over traditional array design methods. To address the realities of process integration, we describe the features and issues associated with integrating this DRAM into SOI technology, including deep trench processing and floating body effects. After a brief description of the macro architecture, details are provided on the three-transistor micro sense amplifier scheme, which is key to achieving a high transfer ratio with minimal area overhead. The paper concludes with hardware results and a summary.

The parasitic bipolar amplification of silicon on insulator (SOI) devices is analyzed as a function of the technology integration from 0.8 /spl mu/m down to 0.1 /spl mu/m. Experiments and simulations show that the bipolar gain does not increase with technology downscaling. The body tie efficiency, to reduce the bipolar amplification, is measured on both transistors and circuits. Implications on the dose rate hardness are deduced on registers with and without body ties as a function of the SOI technology integration.