Essentials of SOI technology for small power supply applications

A SOI (silicon-on-insulator) process using ELO (epitaxial lateral overgrowth) is presented that can be used not only to create local area SOI islands but full wafer SOI as well. A thin full-wafer SOI structure formed with merged ELO has been demonstrated. With minor modification, this SOI process can be successively repeated to produce multiple layers of SOI for future three-dimensional application, since ELO has the advantages of low-temperature processing, ease of interlayer connection, and low cost. This process produces SOI material of very low defect density by using selective epitaxial growth of silicon as compared to other conventional SOI techniques. >

Novel SOI (Silicon On Insulator) model parameter extraction methodology based on the concept of SHE (Self-Heating Effect) free device modeling, is proposed and demonstrated for a 0.18 /spl mu/m PD (Partially Depleted) SOI technology. In this methodology, prior to SPICE parameter extraction, the device thermal resistances are measured and the current loss due to SHE is added back analytically to DC I-V data. Therefore, the parameters are free from SHE. DC, AC, and transient simulation results using this technology show good agreement with measurement data.

As microprocessors enter the highly multi-core/multi-threaded era, higher density, lower latency embedded memory will be required to meet cache design needs. This paper describes a 500 MHz random cycle silicon on insulator (SOI) embedded DRAM macro which features a three-transistor micro sense amplifier, realizing significant performance gains over traditional array design methods. To address the realities of process integration, we describe the features and issues associated with integrating this DRAM into SOI technology, including deep trench processing and floating body effects. After a brief description of the macro architecture, details are provided on the three-transistor micro sense amplifier scheme, which is key to achieving a high transfer ratio with minimal area overhead. The paper concludes with hardware results and a summary.

A 250 V thin-layer SOI technology based on a 1.5-μm-thick SOI layer is developed for high-voltage (HV) switching IC. HV thin-layer silicon on insulator (SOI) field p-channel LDMOS (pLDMOS) with thick gate oxide layer, SOI RESURF n-channel LDMOS (nLDMOS) with thin gate oxide layer, and low-voltage CMOS are monolithically integrated. Compared with the conventional SOI technology integrating field pLDMOS, the thickness of SOI layer is reduced from above 5 μm to only 1.5 μm. The field implant (FI) technology is adopted to eliminate channel discontinuity underneath the bird's beak and achieve shallow junction depth to avoid back gate (BG) punchthrough breakdown for the field pLDMOS. A BG punchthrough model is presented with simulation results. The field pLDMOS with breakdown voltage (BV) of -329 V and RESURF nLDMOS with BV of 338 V are experimentally realized. A 250 V switching IC using the field pLDMOS and RESURF nLDMOS as the level-shift and the output stage is also presented based on the developed thin-layer SOI technology.

By utilizing a lumped-multilayer-based method, we have studied the thermal behavior of a generalized rectangular macro with an extremely high power density of 2500 W/cm/sup 2/ on a microprocessor chip of average power density 40 W/cm/sup 2/. We consider both conventional bulk Si CMOS technology and silicon on insulator (SOI) CMOS. Practical features, including the presence of realistic packaging and interconnect structures are thoroughly analyzed. We found that the worst case temperature rise for such a hotspot is about 11% (/spl sim/7/spl deg/C) above the global chip temperature rise (/spl sim/80/spl deg/C) for 2500 W/cm/sup 2/ power density in SOI technology. As a result of the presence of buried oxide, the thermal behavior of a 15/spl times/300 /spl mu/m/sup 2/ macro in bulk technology is significantly different from SOI technology. It is also found that the existence of the interconnect layers and a solder ball optimally positioned right above the heated macro enables the heat flow to spread horizontally above the macro before eventually being dissipated downwardly toward the heat sink, thus decreasing the peak temperature rise of the macro in the device plane.

In this paper, the noise properties of transistors on 90 nm silicon on insulator (SOI) and bulk CMOS technologies are investigated. At 20 GHz, the SOI and bulk devices have minimum noise figures of 1 dB and 2.3 dB, respectively, demonstrating the superior performance of the SOI technology. The corresponding maximum available gain is 13 dB and 12 dB, respectively. For the first time, the drain and gate noise coefficients of shortchannel SOI devices are extracted yielding values of 2.15 and 1.7, respectively. Theoretical aspects are discussed to identify the main noise sources and to gain insights for optimizations. Furthermore, examples of analog monolithic integrated circuits fabricated on SOI technology are presented. Measured results are a noise figure of 4 dB for a low noise amplifier (LNA) at 40 GHz, a single side band noise figure of 9 dB for a passive mixer at 40 GHz and a phase noise of -90 dBc at 1 MHz offset for an voltage controlled oscillator (VCO) at 60 GHz. To the knowledge of the authors, these are the best noise performances achieved to date for CMOS based transistors and circuits at millimeter wave frequencies.

Silicon on insulator (SOI) has emerged as a high-leverage technology for a wide range of commercial and military applications. While the use of SOI is presently limited to special niche applications, such as radiation-hard space and defense electronics, thin-film SOI has become strategic for low-power, battery-operated portable systems and large-scale integrated logic and memory circuits with sub-half micron features. Substantial process simplification and cost reduction result from the dielectrically isolated structures. Other important SOI applications are the merger of several functions on the same die that performs reliably in adverse high-temperature environments. These include analog and logic functions, smart micromechanical sensors for automotive and distributed jet engine control with logic functions, or smart high-voltage CMOS logic/control elements. Manufacturable solutions to several material and device problems, however, must be demonstrated before SOI CMOS or BiCMOS designs enter the high-volume commercial manufacturing stage. Among these are the availability, cost, and quality of SOI material, gettering, electrostatic discharge protection, the floating-body problem in thin-film structures, and self-heating effects caused by the low thermal conductivity of the buried-oxide layer. The status of SOI material is discussed, including the different methods used to prepare large SOI wafers, wafer availability, cost reduction strategies, material characterization, and material quality. Applications and leverage areas are also described, with emphasis on problems and challenges that lie ahead for the large-scale manufacture of SOI products. The potential economic impact of SOI technology on the profitability of semiconductor manufacturing is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, we present an accurate high-frequency characterization of AC output conductance method to separate SOI specific floating-body effects (FBE) and self-heating effects (SHE) from DC I-V data. In DC measurement, the transistor TEG pattern dependence is essential in view of the SOI body potential, which is confirmed by 3-dimensional device simulation. In AC measurement, the power of small-signal is the most critical issue for removing the FBE and SHE components.

In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. The model uses a single expression to model the channel current, thereby ensuring continuous transition between all operating regions. Furthermore, care has been taken to ensure that this expression is also infinitely differentiable, resulting in smooth and continuous conductances and capacitances as well as higher order derivatives. Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. Small geometry effects such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), charge sharing, and high field mobility effects have also been included. Self-heating (SH) effects are much more apparent in SOI devices than in equivalent bulk devices. These have been modeled in a consistent manner, and the implementation in SPICE3f5 gives the user an additional thermal node which allows internal device temperature rises to be monitored and also accommodates the modeling of coupled heating between separate devices. The model has been successfully used to simulate a variety of circuits which commonly cause problems with convergence. Due to its inherent robustness, the model can normally achieve convergence without recourse to the setting of initial nodal voltage estimates.

We have fabricated monolithic pixel sensors in 0.2 μm Silicon-On-Insulator (SOI) CMOS technology, consisting of a thick sensor layer and a thin circuit layer with an insulating buried-oxide, which has many advantages. However, it has been found that the applied electric field in the sensor layer also affects the transistor operation in the adjacent circuit layer. This limits the applicable sensor bias well below the full depletion voltage. To overcome this, we performed a TCAD simulation and added an additional p-well (buried pwell) in the SOI process. Designs and preliminary results are presented.

The sensitivity to heavy ions of nonhardened 0.25-/spl mu/m partially depleted (PD) silicon on insulator (SOI) and bulk technologies is studied with experiments, device, and circuit simulations. Comparable threshold linear energy transfer (LET) are found for both technologies. Nevertheless, SOI saturated cross section is much lower than bulk one. For nonhardened technologies, SOI is then less sensitive than bulk to heavy ions.

This paper describes the fabrication and the performance analysis of 65 nm PMOS using Silicon‐on‐Insulator (SOI) technology. As the technology evolved towards minimizing the scaling size, the scaling activity has it own limitations. The Silicon‐on‐Insulator (SOI) is the primary method used to overcome the scaling limitation. In this paper, the 65 nm PMOS device with 0.4 μm thickness of Silicon‐on‐Insulator (SOI) Technology was fabricated and the performance of the devices was analyzed by focusing on the electrical characteristics of Id‐Vd and Id‐Vg curves for bulk PMOS and the one with SOI technology. The fabrication process simulation and electrical characteristic was simulated using SILVACO TCAD ATHENA and ATLAS simulator. A very promising results were obtained, the device with SOI technology shows improvement in drain saturation current of Idsat = −269 uA/um from −257 uA/um of bulk PMOS (with increment of 4.7%) and the SOI device exhibits lower threshold voltage of pVth(SOI) = −0.2165 V compared to pVt...

Monolithic active pixel detectors fabricated in SOI (silicon on insulator) technology are novel sensors of ionizing radiation which exploit SOI substrates for the integration of readout electronics with a pixel detector. The fully-depleted sensing diode is manufactured under the SOI buried oxide (BOX) in the volume of the `handle wafer', while readout circuitry occupies the upper silicon SOI `device layer'. However, the initial prototypes suffered from significant leakage currents and early breakdown of pixel diodes. These effects limited the production yield. Moreover, the p-wells within the device layer extended to the interface with the BOX, which caused some local potential wells below the BOX at the top of the depleted sensor area. As a result, the effective charge collection efficiency was significantly decreased. This paper describes a solution for these problems employing a thicker 4 ¿m SOI device layer. The use of this detector structure has increased the effective charge collection efficiency to over 99%.

This technical paper investigates the electrical analysis in sub 90 nm of PMOS. The investigation was carried out by using two different methods which is PMOS with strained silicon and Silicon‐on‐Insulator (SOI) technology. Strained silicon engineering has become a key innovation to enhance device on current. Recently, SOI technology has been widely accepted for use in mainstream high performance logic applications due to some advantageous offered over the bulk silicon. The performance of the devices is analyzed by focusing on the electrical characteristics of Id−Vd and Id−Vg curves for three different structures. Firstly, PMOS with strained silicon of Si3N4 capping layer covering the gate area and secondly the device with and without SOI technology. The fabrication process simulation was simulated by using SILVACO TCAD ATHENA simulator and the electrical characteristic was simulated by SILVACO TCAD ATLAS simulator to obtain Id−Vd and Id−Vg curves. A fruitful and knowledgeable results were reported from this paper, it could be seen that high tensile strain introduced to the device causing the drain current to decreased from Id(bulk) = −400 uA/um of bulk to Id(Strain) = −310 uA/um which is about 25% of decrement. Since the drain current decreased, the carrier mobility and the performance also decreased proportional to drain current. However when SOI technology is applied to the PMOS device, the drain current was increased up to Id(SOI) = −431 uA/um over the bulk, the increment of about 9.25% reported. A higher Id−Vg curve and lower threshold of about pVth(SOI) = −0.2178 V also reported from this paper which tells that the device with SOI technology exhibits low power consumption device and fast switching which in turns contribute to a faster performance.

This paper describes multiple field-coupled simulations and device characterization of fully CMOS-MEMS-compatible smart gas sensors. The sensor structure is designated for gas/vapour detection at high temperatures (>300 °C) with low power consumption, high sensitivity and competent mechanic robustness employing the silicon-on-insulator (SOI) wafer technology, CMOS process and micromachining techniques. The smart gas sensor features micro-heaters using p-type MOSFETs or polysilicon resistors and differentially transducing circuits for in situ temperature measurement. Physical models and 3D electro-thermo-mechanical simulations of the SOI micro-hotplate induced by Joule, self-heating, mechanic stress and piezoresistive effects are provided. The electro-thermal effect initiates and thus affects electronic and mechanical characteristics of the sensor devices at high temperatures. Experiments on variation and characterization of micro-heater resistance, power consumption, thermal imaging, deformation interferometry and dynamic thermal response of the SOI micro-hotplate have been presented and discussed. The full integration of the smart gas sensor with automatically temperature-reading ICs demonstrates the lowest power consumption of 57 mW at 300 °C and fast thermal response of 10 ms.