Silicon on insulator-an emerging high-leverage technology

An SOI-DRAM test device was fabricated on thin-film SOI (Silicon On Insulator) structure with 0.5 /spl mu/m CMOS/SIMOX (Separation by IMplanted OXygen) technology. Field-shield isolation and polysilicon pad techniques were introduced for the specific problems to thin-film SOI devices such as the floating body effects and increase of parasitic source/drain resistance, respectively. Keeping the thin-film SOI from etching off during DRAM cell processing was especially cared by using high-selectivity ECR etching technology. The bit-line capacitance of the experimental SOI-DRAM is reduced by 25% and the /RAS access time is 30% faster compared with the equivalent Bulk-Si DRAM. Low voltage DRAM operation down to 2 V range is also observed. >

Due to the low thermal conductivity of the buried oxide underneath the thin-film silicon layer and the shallow-trench-isolation (STI) structure on the insulating layer, electrostatic discharge (ESD) robustness of CMOS devices in silicon-on-insulator (SOI) CMOS technology has become a major reliability challenge (Chan et al., 1994; Raha et al., 1999; Smith, 1998). As SOI technology continues to be scaled down, the thickness of the top layer silicon film is decreased, and the junction area for ESD protection devices to discharge ESD current becomes smaller. Therefore, the ability to dissipate the heat generated by ESD events in SOI CMOS ICs is seriously degraded. In this paper, two novel diode structures with effective larger p-n junction area for better heat dissipation in partially-depleted SOI CMOS technology are proposed. The I-V characteristics and ESD robustness of these new diodes are investigated and compared to that of the Lubistor diode (Voldman et al., 1996).

A low-power DC-7-GHz distributed amplifier design with on-chip inductor models was realized in a 0.35-/spl mu/m silicon on insulator (SOI) CMOS process. The amplifier has simulated unity-gain cutoff frequency of 7 GHz. The gain is 5.8 dB, with a gain flatness of /spl plusmn/0.7 dB over the DC-6.3-GHz range. The noise figure minimum value is 3.4 dB occurring at 2.8 GHz. At 6.3 GHz, the noise figure is 6 dB. The input-referred 1-dB compression point varies in the range of 10-3 dBm from DC to 7 GHz. Total power dissipation is 50 mW from a 3-V drain supply voltage. This distributed amplifier features as the first design realized in SOI CMOS and with the lowest power dissipation claimed so far.

This paper reports on preliminary results in the production of novel silicon micromachined structures in thick Silicon On Insulator (SOI) at DERA (Malvern). Significant interest in SOI for micromachining has existed for several years, however, until recently the quality of SOI material was not sufficiently high to make it a viable alternative to mainstream bulk silicon technology. Specially designed thick SOI layers have been deep dry etched and structures released to demonstrate the applicability of the material and etch technique to micromachining. An exciting combination of the advantages of both surface and bulk micromachining is offered by SOI. The process used is fully compatible with CMOS and it is thought that the SOI material will become of major importance in many areas of micromachining, particularly micro-inertial components.

Circuit simulation models for thin-film silicon-on-insulator (SOI) MOSFETs have been available for some time. However, these do not take account of the increasingly important self-heating effects that have been widely reported. These effects can lead to a significant reduction in the drain current resulting in negative differential resistance (NDR) in the I/V characteristics of SOI devices. Moreover, recent work has shown that thermal self-heating can also affect transient and small-signal behaviour. Here, we describe the implementation of a model in the SPICE3 code which has been developed to include thermal effects as well as some of the other common characteristics observed in SOI devices. Results of trial simulations are then presented. >

Novel SOI (Silicon On Insulator) model parameter extraction methodology based on the concept of SHE (Self-Heating Effect) free device modeling, is proposed and demonstrated for a 0.18 /spl mu/m PD (Partially Depleted) SOI technology. In this methodology, prior to SPICE parameter extraction, the device thermal resistances are measured and the current loss due to SHE is added back analytically to DC I-V data. Therefore, the parameters are free from SHE. DC, AC, and transient simulation results using this technology show good agreement with measurement data.

In this paper, the electrostatic-discharge (ESD) protection capabilities of the protection devices fabricated on a silicon-on-diamond (SOD) structure and a conventional Si substrate are compared. The results showed that the ESD protection capability of the SOD substrate is higher than that of the silicon-on-insulator (SOI) substrate. We also evaluate the ESD protection device suitable for the SOD structure. In addition, we propose the three-dimensional (3D) stacking structure suitable for a power supply on a chip (power-SoC) and the best location for the implementation of the ESD protection device based on the results of device simulations.

LSI trends and technological background allowing the full-scale introduction of SOI (Silicon on Insulator) CMOS are described, the features of SOI CMOS and its effectiveness for achieving low power consumption and high speed of LSIs are summarized, and application examples are presented. In connection with the future prospects of SOI CMOS, descriptions of parasitic effects, which are becoming more prominent with scaling, device structures capable of suppressing them, concepts of performance improvement under the future trend of supply voltage lowering, and the necessary technology, are discussed. © 2000 Scripta Technica, Electron Comm Jpn Pt 2, 83(10): 24–34, 2000

This work addresses the design and optimization of high performance CMOS devices in the sub-60 nm regime. Aggressive scaling of the poly gate length is achieved by controlling the short-channel effects in partially-depleted SOI (Silicon-On-Insulator) CMOS devices. In addition, SOI specific design issues are examined to reduce device parasitics such as junction capacitance and history effect through the optimization of silicon film thickness. A high performance SOI CMOS with well-behaved 52 nm gate length devices is demonstrated.

In this paper, we propose a novel Silicon on Insulator (SOI) Metal Semiconductor Field Effect Transistor (MESFET) with an embedded GaN layer (GL-SOI-MESFET) for modifying the electric field distribution. The main idea of this work is based on using a high breakdown field material (GaN), for amending the electric field and potential distribution near the drain region, and as a result, the breakdown voltage of the proposed structure will be higher than a conventional structure (C-SOI-MESFET). The breakdown voltage (VBR) of the GL-SOI-MESFET at the Ids = 55 mA/mm and Vgs = − 1 V has been achieved ~21 V whereas the VBR in the C-SOI-MESFET is 16 V. The proposed structure shows the improvement of DC and RF characteristics versus the C-SOI-MESFET. For obtaining the best results to improve the structure performance, dimensions of the GaN layer have been optimized. Also, by amending potential distribution and changing the depletion region between the gate and drain sides, the gate-drain capacitance reduces. The effects like the electric field, the potential distribution, breakdown voltage, the kink effect, the self-heating effect, power gains, and parasitic capacitances are investigated and the proposed structure results have superior DC and radio frequency (RF) performances compared with the conventional MESFET structure.

In this paper, the Self Heating Effect (SHE) is investigated in silicon on insulator (SOI) nanowire MOSFETs. A comprehensive study of SHE in Nanowire FET (NWFET) was implemented by Technology Computer-Aided Design (TCAD) simulation. Through analysis of on-current (ISUBon/SUBSUB/SUB), thermal resistance (RSUBTH/SUB), and heat flux, the DC characteristics of SHE were investigated according to the increase of buried oxide thickness (Tbox). The results indicate that leakage current is not changed according to Tbox so that it is not necessary to increase TSUBbox/SUB. In conclusion, in case that TSUBbox/SUB was optimized by 1 nm, temperature and RSUBTH/SUB were reduced by 152 K and 54.5% respectively. Also, ISUBon/SUB was increased by 5.84% maintaining leakage current compared with Tbox of 20 nm.

As it becomes more difficult to increase MOSFET current drive through standard scaling techniques, other methods to improve performance are being pursued. One such technique is to use silicon-on-insulator (SOI) starting wafers. Performance enhancements using SOI have been demonstrated by a number of authors. Most of the reported work has used SIMOX material. Bonded SOI material is an alternative to SIMOX, which potentially has lower material defect density. The purpose of this work was to compare bonded SOI performance and yield to that of bulk CMOS.

The influence of back-gate bias on DC and RF characteristics in C-doped SiGe HBTs (SiGe:C HBTs) on thin-film silicon-on-insulator (SOI) was investigated. The experimental result indicates that a positive substrate bias is very effective in R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> and hysteresis reduction, and further improves the maximum f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> from 16 to 53GHz. Analytical relationships are developed to quantify the impact of substrate bias on electrical characteristics, which further approved by calibrated Sentaurus simulations.

Silicon-on-Insulator (SOI) technology has evolved from being exclusively devoted to “niche” market areas as radiation hard or high temperature applications to recently becoming a player in the high performance digital circuits market [IBM011, IBM012]. In addition, the international semiconductor community sees the fully-depleted (FD) variety, which is the one tested in this work, as one of the strong alternatives for solving the transistor scaling challenges in next generations of very deep sub micron processes [ITR01]. We will summarize here the characteristics of the type of SOI MOS devices used in this work, in order to compare later the performance of FD SOI and bulk CMOS analog blocks in low-voltage, micropower applications. This comparison is particularly focused on those blocks and performance aspects that are central to the proposed implementation of our study vehicle, the sense channel, as well as to the implementation of other pacemaker analog blocks. This is the case of the speed and precision of current mirrors, which are essential elements in the class AB stage proposed in Chapter 5, and of OTA characteristics such as the power-bandwidth trade-off, noise and offset.

A tunnel diode body contact (TDBC) silicon-on-insulator (SOI) MOSFET structure without floating-body effects (FBEs) is proposed and successfully demonstrated. The key idea of the proposed structure is that a tunnel diode is embedded in the source region, so that the accumulated carriers can be released through tunneling. In an n-MOSFET, a heavily doped p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> layer is introduced beneath the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> source region. The simulated and measured results show the suppressed FBE, as expected. Other phenomena that originate from the FBEs, such as the kink, linear kink effect, abnormal subthreshold swing, and small drain-tosource breakdown voltage in the properties, were also sufficiently suppressed. In addition, it should be noted that the proposed SOI MOSFETs are fully laid out and process compatible with SOI CMOS. Hysteresis effects disappear in TDBC SOI MOSFETs, which makes them attractive for digital applications. On the other hand, in analog applications, TDBC SOI MOSFETs are shown to hold the advantage over floating-body SOI MOSFETs due to their higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Gm</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ID</i> ratio. TDBC SOI MOSFETs can be considered as one of the promising candidates for digital and analog devices.