ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation

Silicon on insulator (SOI) has emerged as a high-leverage technology for a wide range of commercial and military applications. While the use of SOI is presently limited to special niche applications, such as radiation-hard space and defense electronics, thin-film SOI has become strategic for low-power, battery-operated portable systems and large-scale integrated logic and memory circuits with sub-half micron features. Substantial process simplification and cost reduction result from the dielectrically isolated structures. Other important SOI applications are the merger of several functions on the same die that performs reliably in adverse high-temperature environments. These include analog and logic functions, smart micromechanical sensors for automotive and distributed jet engine control with logic functions, or smart high-voltage CMOS logic/control elements. Manufacturable solutions to several material and device problems, however, must be demonstrated before SOI CMOS or BiCMOS designs enter the high-volume commercial manufacturing stage. Among these are the availability, cost, and quality of SOI material, gettering, electrostatic discharge protection, the floating-body problem in thin-film structures, and self-heating effects caused by the low thermal conductivity of the buried-oxide layer. The status of SOI material is discussed, including the different methods used to prepare large SOI wafers, wafer availability, cost reduction strategies, material characterization, and material quality. Applications and leverage areas are also described, with emphasis on problems and challenges that lie ahead for the large-scale manufacture of SOI products. The potential economic impact of SOI technology on the profitability of semiconductor manufacturing is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this study, we fabricated thermopile infrared sensor with floating membrane structure. Floating membrane was formed by SOI(Silicon On Insulator) structure. In SOI structure, silicon dioxide layer between top silicon layer and bottom silicon substrate was etched by HF solution, then membrane was floated over substrate. After membrane was floated, thermopile pattern was formed on membrane. By insertion of SOI technology, we could obtain thermal isolation structure easily and passivation process for sensor pattern protection was not required during fabrication process. Then, the amplifier circuit for thermopile sensor was fabricated by using <TEX>$1.5{\mu}m$</TEX> CMOS process. The voltage gain of fabricated amplifier was about two hundred.

A high resolution IR microscope, especially designed for measuring localized joule heating effect in silicon devices, has been developed by combining a ZnS objective lens and a HgCdTe infrared detector. This microscope has achieved the practical spatial resolution of 10 mu m and practical temperature resolution of 0.24 K. With this IR microscope, the joule heating effect in poly-Si (polycrystalline silicon) thin film resistors formed on SiO/sub 2/ thin layer has been measured, simulating SOI (silicon on insulator) structures. A significant temperature rise was observed in this device structure, because of the low thermal conductivity of the SiO/sub 2/ layer, suggesting the possibility of new reliability problems caused by the joule heating effect in SOI structures. >

Effect of high temperature - pressure on SOI structure

The influence of back-gate bias on DC and RF characteristics in C-doped SiGe HBTs (SiGe:C HBTs) on thin-film silicon-on-insulator (SOI) was investigated. The experimental result indicates that a positive substrate bias is very effective in R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> and hysteresis reduction, and further improves the maximum f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> from 16 to 53GHz. Analytical relationships are developed to quantify the impact of substrate bias on electrical characteristics, which further approved by calibrated Sentaurus simulations.

The current-voltage characteristics and the carrier-transport mechanism of the Er-silicide (ErSi1.7) Schottky contacts to strained-silicon-on-insulator (sSOI) and silicon-on-insulator (SOI) were investigated. Barrier heights of 0.74 eV and 0.82 eV were obtained for the sSOI and SOI structures, respectively. The barrier height of the sSOI structure was observed to be lower than that of the SoI structure despite the formation of a Schottky contact using the same metal silicide. The sSOI structure exhibited better rectification and higher current level than the SOI structure, which could be associated with a reduction in the band gap of Si caused by strain. The generation-recombination mechanism was found to be dominant in the forward bias for both structures. Carrier generation along with the Poole-Frenkel mechanism dominated the reverse-biased current in the SOI structure. The saturation tendency of the reverse leakage current in the sSOI structure could be attributed to strain-induced defects at the interface in non-lattice-matched structures.

This paper describes a new way to suppress the floating body effect (FBE) in SOI MOSFETs, which is applicable to the CMOS structure. The FBE can be suppressed by controlling the potential profile in the lower body region of SOI MOSFETs. The threshold voltage (V<SUB>T</SUB>) of SOI NMOSFETs little depends on drain voltage (V<SUB>D</SUB>) when impact ionization is not significant. V<SUB>T</SUB> is determined by the total body charge. On the contrary, when impact ionization significantly occurs, V<SUB>T</SUB> largely depends on V<SUB>D</SUB>. The accumulation of holes in a floating body raises the body bias, and thus the increase in the body bias determines V<SUB>T</SUB>. From the examination of the influence of a substrate voltage (V<SUB>SUB</SUB>), it is clarified that there is a maximum value of V<SUB>SUB</SUB> (V<SUB>SUB,MAX</SUB>) below which the V<SUB>T</SUB> measured at V<SUB>D</SUB> higher than 1 V does not depend on V<SUB>SUB</SUB>. It is also clarified that the dependence of V<SUB>T</SUB> on V<SUB>D</SUB> can be drastically improved by supplying a V<SUB>SUB</SUB> that is higher than V<SUB>SUB,MAX</SUB>. This means that supplying an adequate V<SUB>SUB</SUB> is effective in suppressing the FBE. Holes accumulated in the NMOS body region are significantly decreased by the V<SUB>SUB</SUB> supply, which is supported by 2D device simulation, and hence the FBE in SOI NMOSFETs is suppressed. Supplying positive V<SUB>SUB</SUB> little affects the PMOSFETs characteristics, except for an increase in V<SUB>T</SUB>. Therefore, this method is useful for the SOI CMOSFET structure.

In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. The model uses a single expression to model the channel current, thereby ensuring continuous transition between all operating regions. Furthermore, care has been taken to ensure that this expression is also infinitely differentiable, resulting in smooth and continuous conductances and capacitances as well as higher order derivatives. Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. Small geometry effects such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), charge sharing, and high field mobility effects have also been included. Self-heating (SH) effects are much more apparent in SOI devices than in equivalent bulk devices. These have been modeled in a consistent manner, and the implementation in SPICE3f5 gives the user an additional thermal node which allows internal device temperature rises to be monitored and also accommodates the modeling of coupled heating between separate devices. The model has been successfully used to simulate a variety of circuits which commonly cause problems with convergence. Due to its inherent robustness, the model can normally achieve convergence without recourse to the setting of initial nodal voltage estimates.

The floating-body effect (FBE) in nonfully-depleted (NFD) SOI MOSFETs gives rise to excess low-frequency noise. For the first time, the origin of the excess noise is identified to be the shot noise associated with impact ionization current and body-source diode current. The shot noise, normally negligible as compared with flicker noise, is amplified in the device through FBE. The noise model predicts that the excess low-frequency noise shows a Lorentzian-like spectrum as verified by experimental data. The physical explanation is further supported by the coincidence of the corner frequency in the noise spectrum and the AC output impedance.

The IR properties in SOI wafers formed by oxygen implantation into silicon

The authors have developed a novel technique for obtaining bulk quality thin-film SOI (silicon-on-insulator) by wafer bonding and selective polishing. 625- mu m-thick 5-in.-diameter

Tremendous progress in understanding and improving SOI material and devices has been made in recent years. The reduced junction capacitance and the minimal body-effect of SOI provides an inherent advantage for low-voltage low-power applications. Recent growth in the portable wireless communication market and the push for low cost solutions have driven the semiconductor industry into a race for the ultimate solution: a single chip radio capable of handling both the RF and baseband functions. In this paper, the applications of Thin-Film-Silicon-On-Insulator (TFSOI) to the different circuit elements of wireless communication systems are reviewed. The use of CMOS SOI devices as well as future development essential to realize the single chip radio are discussed.

By an improved Al2O3(100) growth on Si(100) using O2 gas instead of N2O gas, high-crystalline quality silicon on insulator (SOI) and multistacked SOI structures were successfully fabricated on a 2-inch Si(100) wafer by the ultrahigh-vacuum chemical vapor deposition (UHV-CVD) method. The surface morphology of the Si top layer of the fabricated SOI structure is better than that of the silicon on sapphire (SOS) structure grown by the UHV-CVD method. The transistor action was confirmed from the electrical properties of the MOSFET, and the field effect mobility of 748 cm2/V s was obtained. These results were similar to those obtained from bulk Si. This improved Si top layer of SOI and multistacked SOI structures is due to the improved surface morphology and crystalline quality of the Al2O3 layer grown on Si with O2 gas.

The relationship between that of silicon-on-insulator (SOI) technology and ordinary CMOS is presented followed with an examination of the basic features of MOSFETs fabricated under the SOI process. Such features include the intrinsic junction diodes, diffusion capacitance, floating-body effect, internal parasitic bipolar effects, the insulation layer and its consequences, and the self-heating effect. In addition to the fact that many of these features provide improvements in transistor design and performance over standard CMOS, SOI technology is poised to become competitive for small power supply applications.

A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given "critical" dose. Above this dose, we still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic conduction is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies.