Thermopile sensor with SOI-based floating membrane and its output circuit

A high resolution IR microscope, especially designed for measuring localized joule heating effect in silicon devices, has been developed by combining a ZnS objective lens and a HgCdTe infrared detector. This microscope has achieved the practical spatial resolution of 10 mu m and practical temperature resolution of 0.24 K. With this IR microscope, the joule heating effect in poly-Si (polycrystalline silicon) thin film resistors formed on SiO/sub 2/ thin layer has been measured, simulating SOI (silicon on insulator) structures. A significant temperature rise was observed in this device structure, because of the low thermal conductivity of the SiO/sub 2/ layer, suggesting the possibility of new reliability problems caused by the joule heating effect in SOI structures. >

Effect of high temperature - pressure on SOI structure

The IR properties in SOI wafers formed by oxygen implantation into silicon

The current-voltage characteristics and the carrier-transport mechanism of the Er-silicide (ErSi1.7) Schottky contacts to strained-silicon-on-insulator (sSOI) and silicon-on-insulator (SOI) were investigated. Barrier heights of 0.74 eV and 0.82 eV were obtained for the sSOI and SOI structures, respectively. The barrier height of the sSOI structure was observed to be lower than that of the SoI structure despite the formation of a Schottky contact using the same metal silicide. The sSOI structure exhibited better rectification and higher current level than the SOI structure, which could be associated with a reduction in the band gap of Si caused by strain. The generation-recombination mechanism was found to be dominant in the forward bias for both structures. Carrier generation along with the Poole-Frenkel mechanism dominated the reverse-biased current in the SOI structure. The saturation tendency of the reverse leakage current in the sSOI structure could be attributed to strain-induced defects at the interface in non-lattice-matched structures.

Implant damage and redistribution of indium in indium-implanted thin silicon-on-insulator

By an improved Al2O3(100) growth on Si(100) using O2 gas instead of N2O gas, high-crystalline quality silicon on insulator (SOI) and multistacked SOI structures were successfully fabricated on a 2-inch Si(100) wafer by the ultrahigh-vacuum chemical vapor deposition (UHV-CVD) method. The surface morphology of the Si top layer of the fabricated SOI structure is better than that of the silicon on sapphire (SOS) structure grown by the UHV-CVD method. The transistor action was confirmed from the electrical properties of the MOSFET, and the field effect mobility of 748 cm2/V s was obtained. These results were similar to those obtained from bulk Si. This improved Si top layer of SOI and multistacked SOI structures is due to the improved surface morphology and crystalline quality of the Al2O3 layer grown on Si with O2 gas.

Research on synthetic-grating SOI structure for simultaneous operation of 1310 and 1550 nanometer signal: A handy proposal of optical interconnect for photonic integrated circuits

Thin silicon-on-insulator (SOI) film formation during 25 keV O+ ion implantation has been investigated by cross-sectional transmission electron microscopy, Auger electron spectroscopy and scanning electron microscopy. The top Si layer thickness in as-implanted samples increased with increasing substrate temperature from 280 to about 500 degrees C and the current density from 10 to 450 mu A cm-2 at a constant dose of 2*1017 ion cm-2. Substrate heated to about 485 degrees C showed remarkable in situ annealing effects during ion implantation; resulting in the oxygen depth profile and the increase of the Si-O bonding. The SOI structure was formed in a wide range of the current density at about 485 degrees C. Shallow holes appearing in the surface at substrate temperatures higher than 485 degrees C scarcely influenced subsequent SOI structure formation. Deep holes appearing above 530 degrees C made it difficult to produce the SOI structure.

Specific features of formation of radiation defects in thin silicon layer of silicon-on-insulator (SOI) structures have been studied. It is shown that there are differences between variations in the structural and electrical properties of the thin silicon layer and those in bulk silicon crystals (with similar electrical characteristics) subjected to the same radiation effect. It is established that the embedded insulator in the SOI structure represents a barrier for motion of radiation-induced intrinsic interstitial silicon atoms, which brings about an increase in the dose of bombarding ions, which leads to the loss of single-crystallinity of the silicon layer in a SOI structure. It is shown that γ-ray irradiation with doses unaffecting the electrical conductivity of bulk silicon crystals appreciably affects the conductivity of the silicon layer in the SOI structures. In addition, variation in the conductivity of silicon layer is related to variation in the density of surface states at the interface between the silicon layer and the built-in insulator, rather than to generation of conventional radiation-induced structural defects in silicon.

An SOI-DRAM test device was fabricated on thin-film SOI (Silicon On Insulator) structure with 0.5 /spl mu/m CMOS/SIMOX (Separation by IMplanted OXygen) technology. Field-shield isolation and polysilicon pad techniques were introduced for the specific problems to thin-film SOI devices such as the floating body effects and increase of parasitic source/drain resistance, respectively. Keeping the thin-film SOI from etching off during DRAM cell processing was especially cared by using high-selectivity ECR etching technology. The bit-line capacitance of the experimental SOI-DRAM is reduced by 25% and the /RAS access time is 30% faster compared with the equivalent Bulk-Si DRAM. Low voltage DRAM operation down to 2 V range is also observed. >

A two-dimensional model is developed of silicon recrystallization by nanosecond laser pulses in a silicon-on-insulator (SOI) structure with seed windows. Using this model, temperature and thermoelastic fields and phase transition behaviour are calculated. Phase transitions are described by new phase nucleation (homo- and heterogeneous) kinetics and its growth. The experimental situation is computerized using ruby laser action with 30 ns pulses and 0 to 3 J/cm2 energy density. The melting depth is shown to be greater at the edge of the seed window than in its center. This causes Si laterial epitaxy, while in the seed area the polycrystal remains. It is predicted that in the crystallization front movement along the dielectric the slope towards the dielectric increases, and the more, the lower the preheating temperature of the sample is. The thermoelastic stresses in the SOI structure are calculated before melting and after cooling, and it is shown that with higher preheating, the residual stresses in the sample are higher. The results of the computations are compared with experimental data. [Russian Text Ignored.]

The fabrication of freestanding SiC microstructures on Silicon-On-Insulator (SOI) and semi-insulating Silicon substrates is reported. SiC layers were grown on SOI and semi-insulating Si by chemical vapour deposition (CVD) and to avoid the instability currently obtained in SOI structures, the growth process parameters have been optimized. Isotropic wet chemical etching of the Si sacrificial layer released the electrostatic SiC microstructures patterned by dry etching. Moreover a new concept for reducing the gap between resonators and electrodes by the uses of bistable mobile electrodes is introduced.

ABSTRACTThis paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

Selective buried oxide (SELBOX) Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) structure can be used to reduce the kink effect and self‐heating problems associated with the silicon on insulator (SOI) MOSFET devices while maintaining the advantages of bulk MOSFET. In this paper, static power dissipation of SELBOX structure is investigated and compared with SOI and bulk structures. Various MOSFET structures are simulated and evaluated in terms of their static power dissipation. Only results from 90‐nm Complementary Metal Oxide Semiconductor (CMOS) technology devices are included in this paper. Simulation results using the Silvaco TCAD show that static power dissipation in SELBOX CMOS is similar to that of SOI devices but lower than that of bulk CMOS. Hence, SELBOX structure is found to produce relatively low‐static power dissipation while maintaining high operating speed and reducing self‐heating and kink effect. A mathematical model to describe the static power dissipation in the subthreshold region is also included. Statistical analysis show that the model and fabrication simulation results agree with P < .05 and correlation coefficient of 0.95.

Buried nitride silicon-on-insulator (SOI) substrates prepared using stationary beam synthesis have been characterized. It is found that surface Si layers and alpha and beta-phase silicon nitride layers of good quality can be formed in the SOI structure if the implant and annealing conditions are suitably controlled. However, the high nitrogen content inside the surface Si layer has been found to create new problems to the direct fabrication of devices on the SOI substrate.