SiC Freestanding Micromechanical Structures on Silicon-On-Insulator Substrates

In this study, we fabricated thermopile infrared sensor with floating membrane structure. Floating membrane was formed by SOI(Silicon On Insulator) structure. In SOI structure, silicon dioxide layer between top silicon layer and bottom silicon substrate was etched by HF solution, then membrane was floated over substrate. After membrane was floated, thermopile pattern was formed on membrane. By insertion of SOI technology, we could obtain thermal isolation structure easily and passivation process for sensor pattern protection was not required during fabrication process. Then, the amplifier circuit for thermopile sensor was fabricated by using <TEX>$1.5{\mu}m$</TEX> CMOS process. The voltage gain of fabricated amplifier was about two hundred.

A high resolution IR microscope, especially designed for measuring localized joule heating effect in silicon devices, has been developed by combining a ZnS objective lens and a HgCdTe infrared detector. This microscope has achieved the practical spatial resolution of 10 mu m and practical temperature resolution of 0.24 K. With this IR microscope, the joule heating effect in poly-Si (polycrystalline silicon) thin film resistors formed on SiO/sub 2/ thin layer has been measured, simulating SOI (silicon on insulator) structures. A significant temperature rise was observed in this device structure, because of the low thermal conductivity of the SiO/sub 2/ layer, suggesting the possibility of new reliability problems caused by the joule heating effect in SOI structures. >

By an improved Al2O3(100) growth on Si(100) using O2 gas instead of N2O gas, high-crystalline quality silicon on insulator (SOI) and multistacked SOI structures were successfully fabricated on a 2-inch Si(100) wafer by the ultrahigh-vacuum chemical vapor deposition (UHV-CVD) method. The surface morphology of the Si top layer of the fabricated SOI structure is better than that of the silicon on sapphire (SOS) structure grown by the UHV-CVD method. The transistor action was confirmed from the electrical properties of the MOSFET, and the field effect mobility of 748 cm2/V s was obtained. These results were similar to those obtained from bulk Si. This improved Si top layer of SOI and multistacked SOI structures is due to the improved surface morphology and crystalline quality of the Al2O3 layer grown on Si with O2 gas.

Effect of high temperature - pressure on SOI structure

The formation of smooth, conformal cobalt disilicide (CoSi2) without facets or voids is critical for microelectronic device reliability owing to the ultra-shallow contact areas. Here we demonstrate the formation of smooth and conformal CoSi2 films by chemical vapor deposition (CVD) of cobalt nitride (CoxN) films on silicon (Si) or on silicon on insulator (SOI) substrates, followed by in-situ rapid thermal annealing (RTA) at 700°C. To reveal the CoSi2/Si interfacial morphology, we report a back-to-front sample preparation method, in which mechanical polishing, anisotropic tetramethylammonium hydroxide (TMAH) wet etching, hydrofluoric acid (HF) wet etching, and isotropic xenon difluoride (XeF2) dry etching are employed to remove the SOI substrate from the back side to expose the CoSi2/Si interface. This method offers a robust and reliable procedure for quantitative assessment of the CoSi2/Si interfacial roughness, as well as analytical support for advanced fabrication process development.

The current-voltage characteristics and the carrier-transport mechanism of the Er-silicide (ErSi1.7) Schottky contacts to strained-silicon-on-insulator (sSOI) and silicon-on-insulator (SOI) were investigated. Barrier heights of 0.74 eV and 0.82 eV were obtained for the sSOI and SOI structures, respectively. The barrier height of the sSOI structure was observed to be lower than that of the SoI structure despite the formation of a Schottky contact using the same metal silicide. The sSOI structure exhibited better rectification and higher current level than the SOI structure, which could be associated with a reduction in the band gap of Si caused by strain. The generation-recombination mechanism was found to be dominant in the forward bias for both structures. Carrier generation along with the Poole-Frenkel mechanism dominated the reverse-biased current in the SOI structure. The saturation tendency of the reverse leakage current in the sSOI structure could be attributed to strain-induced defects at the interface in non-lattice-matched structures.

The IR properties in SOI wafers formed by oxygen implantation into silicon

ABSTRACTWe have made an extensive study of Si0.82Ge0.18 film relaxation on silicon on insulator (SOI) substrates having a top Si layer 40, 70, 330nm, and 10[.proportional]m thick. SiGe films were deposited with a thickness up to 1.2[.proportional]m in an ultrahigh vacuum chemical vapor deposition system at 630°C. Following growth, films were characterized by X-ray diffraction and a dislocation revealing etch. The same level of relaxation is reached for each thickness of SiGe film independent of the substrate structure. Accompanying the film relaxation is the development of a tetragonal tensile strain in the thin Si layer of the SOI substrates. This strain reached 0.22% for the 1.2[.proportional]m film on the 40nm SOI and decreases with SOI thickness. The Si thickness of the SOI substrate also effected the threading dislocation density. For 85% relaxed films the density fell from 7×106 pits/cm2 on bulk Si to 103pits/cm2 for the 40, 70, and 330nm SOI substrates. The buried amorphous layer of the SOI substrate alters the dislocation dynamics by allowing dislocation core spreading or dislocation dissociation. The reduced strain field of these dislocations reduces dislocation interactions and the pinning that results. Without the dislocation pinning, the misfit dislocations can extend longer distances yielding a greatly reduced threading dislocation density.

1. Introduction Ge has been received much attention as the next generation semiconductor materials due to its attractive characteristics such as high carrier mobility[1] and narrow bandgap corresponding near infrared wavelength[2]. In order to utilize its characteristics for the applications, Ge-on-Insulator (GOI) structure is necessary. Several fabrication methods for GOI have been suggested such as wafer bonding and mechanical thinning[3], Smart-CutTM[4,5], and SiGe condensation[6]. It is well known Smart-CutTM is widely used for commercial Si-on-Insulator (SOI) fabrication. However, Ge is more sensitive to damages caused by ion implantation and difficult to recover damages completely. Therefore, the best way for GOI fabrication have not been developed.In early stage of SOI R&D, many approaches were proposed, too[7]. Wafer bonding and etchback is one of the simplest technique, and the advantage of this method is any damages due to ion implantation or mechanical stress are not induced to the top semiconductor layer. Therefore, we focused on etchback technique for GOI fabrication. It is necessary to develop appropriate Ge etching method with moderate etching rate and keeping or improving surface flatness. In this study, we aim to develop appropriate etching method of Ge for etchback GOI fabrication. 2. Experimental and results We used single side mirror polished Ge wafer with a thickness of 500 μm. Figure 1 shows the experimental procedure in this study. The original polished top surface was covered by photoresist to avoid etching from this side. Firstly, we confirmed HF + HNO3 mixture solution for Ge etching because it is widely known as etching solution for Si. Figure 2 shows optical microscope images for the back side (non-polished side) of (100)-oriented Ge wafer (a) before etching and (b) after etching by HF + HNO3 for 7 minutes. By etching, surface uniformity drastically improved. So, wet etching can be used for Ge thinning and planarization. However, this solution reacts handle Si substrate of GOI, too. As an alternative etching solution, we selected HF + H2O2 mixture[8]. Figure 3 shows the etching result of (100)-oriented Ge etched by HF + H2O2 + H2O (7:7:6) solution. Although Ge was etched similar to Fig. 2(b), surface uniformity was inferior to HF + HNO3 etching. To improve surface uniformity, CH3COOH was added as diluent instead of H2O because politic amount of CH3COOH into HF + HNO3 solution leads isotropic etching and mirror plane on Si surface[9]. Figures 4 shows the etching results of (100)-oriented Ge by HF + H2O2 + CH3COOH (1:1:1) solution. Surface uniformity improved than Fig. 3 and there is no orientation dependence (data not shown). Therefore, isotropic etching occurs on Ge surface. The average etching rate in the first 20 minutes calculated from the lost masses was 7.9 μm/min. It should be noted any agitation was not carried out during etching and longer etching time leads decreasing of etching rate. Possible etching reaction is expressed as[10]:2CH3COOH + 2H2O2 → 2CH3COOOH + 2H2O (1)Ge + 2CH3COOOH + 2e - → Ge2+ + 2CH3COO- + 2OH- (2)As further investigation of surface uniformity, atomic force microscope (AFM) observation was carried out. Figure 5 shows AFM images for backside of (100)-oriented Ge etched for 110 minutes. The RMS of 30×30 μm2 area is 0.48 nm. Compared with the RMS of original backside (> 5 μm), the surface flatness is improved drastically. In the conference, electrical characteristics of etched surface will be presented. 3. Conclusions For etchback GOI fabrication, we study isotropic etching for Ge. HF + H2O2 + CH3COOH mixture solution can etch Ge isotropic and improving surface uniformity. This solution has a potential as etching solution for etchback to make GOI structure. Acknowledgements This work was supported by JSPS KAKENHI Grant Numbers 19K15028 and 19H05616. Appendix Original concentrations of the chemicals in this study are HF: 49 wt%, HNO3: 69 wt%, H2O2: 30 wt%, and CH3COOH: 99.7 wt%. All compounding ratios in this article are volume rate.

Background: CR-39 nuclear track detectors are widely used in various fields, including science, technology, astronomy, and environmental preservation, to detect and register heavy ions, neutrons, and alpha particles. Objective: This study aims to determine the optimal etching duration for CR-39 nuclear track detectors by comparing etching methods: The wet etching (using a water bath) and the dry etching technique (using dielectric barrier discharge (DBD) plasma). Methods: The traditional etching method involved immersing CR-39 detectors in a sodium hydroxide (NaOH) solution at 70 °C for varying durations. The dry etching method employed employs a non-thermal DBD plasma system to etch solid-state nuclear track detectors (SSNTDs) without the use of chemical solutions. Results: Photomicrographs revealed that tracks from chemical etching became clearly visible after 1 hour and developed at 5 hours. In contrast, the dry etching technique was significantly faster; tracks began to appear after just 1 minute of DBD plasma etching and were fully developed at 5 minutes. The optimum track density for DBD plasma was 20340±56 tracks/mm2 at 3 minutes, whereas the traditional water bath method achieved an optimum track density of 5238.0±5.7 tracks/mm2 at 2 hours. The shorter etching duration in the dry method likely facilitates the emergence of latent tracks without overlap. Conclusions: The bulk etch rate (VB) for CR-39 detectors using the dry DBD plasma etching technique was faster compared to the traditional chemical etching method. This demonstrates the efficacy of the dry etching process in significantly reducing etching time required for etching SSNDs.

An SOI-DRAM test device was fabricated on thin-film SOI (Silicon On Insulator) structure with 0.5 /spl mu/m CMOS/SIMOX (Separation by IMplanted OXygen) technology. Field-shield isolation and polysilicon pad techniques were introduced for the specific problems to thin-film SOI devices such as the floating body effects and increase of parasitic source/drain resistance, respectively. Keeping the thin-film SOI from etching off during DRAM cell processing was especially cared by using high-selectivity ECR etching technology. The bit-line capacitance of the experimental SOI-DRAM is reduced by 25% and the /RAS access time is 30% faster compared with the equivalent Bulk-Si DRAM. Low voltage DRAM operation down to 2 V range is also observed. >

Surface machining processes are responsible for creating microstructures that reside near the surfaces of a substrate and are characterized by the fabrication of micromechanical structures from deposited thin films. These films can be selectively removed to build three-dimensional structures whose functionality typically requires that they should be freed from the planar substrate. Silicon nitride thin film is one of these important materials. In this paper, by adjusting the SiH2Cl2/NH3gaseous ratio, low stress silicon nitride (LS SiN) is deposited by the low pressure chemical vapor deposition (LPCVD) process. The internal stress generally in 135 MPa has been detected using an FLX-2320 film stress tester. Based on the wide application in surface micromachining devices, the mechanical properties of LS SiN are measured by nanoindentation, giving the value of Young’s modulus of 224 GPa and the hardness of 22.5 GPa, respectively. Dry etching and wet etching are utilized to fabricate the LS SiN thin film for structural layers. The etching rate compared with normal Si3N4film by LPCVD is demonstrated for silicon chip manufacture.

Uncooled thermal detectors for infrared (IR) sensing have attracted attention for both military and civil applications. One of the evaluation parameters for a high performance bolometer is thermal coefficient resistance (TCR). During the last decade monocrystalline SiGe is presented as a new generation of low cost thermistor materials. [1] Although the SiGe thermistor materials, based on multilayer quantum well (MQW) structures, have been investigated for a few years, so far none of the reports have been able to evaluate TCR values rapidly due to the complicated process and compatibility with available tools. In this paper, we report a relatively facile microfabrication process of self-doping SiGe/Si MQW thermoelectrical arrays as well as their thermoelectrical properties.A 4-inch SOI wafer was used as the handle wafer for the growth of SiGe/Si MQWs. The thickness of silicon handle wafer part silicon on insulator (SOI) wafer is 500 μm with 1.5 μm BOX layer (SiO2). The total 5 periodic thickness of SiGe/Si MQW is 725 nm and grown on the SOI wafer, and then sputtered with 20 nm Ti layer and 70 nm Al layer sequentially. Then a second patterned metallized wafer was electroplated with Au interconnect lines and pads as electrical measurement leads. The two wafers were then bonded together face to face using a wafer-level adhesive wafer bonding [2]. After the bonding, the 500 μm thick Si layer of SOI wafer was removed by inductively coupled plasma (ICP) Etching etching. The ICP stops at the SiO2 layer, and the SiO2 is removed by using regular BOE (buffer oxide etches). The SiGe/Si film was then patterned by lithography and dry etching. With the electroplated Au electrode column connecting the film and the Au pads on target wafer, the thin film was then covered by the 50nm Ti by sputter and the 350nm SiN layer deposited by PECVD for enhancing infrared light absorption. Finally, the whole device layer was patterned by lithography and dry etching, during which the bonding polymer was completely removed by O2 plasma. The released arrays are shown in fig.1. Then, the dependence of current-resistance and the temperature-resistance are examined by the facile metallized leads and the results are shown in fig.2. The TCR (temperature coefficient of resistance) of the arrays is about -2.6%K-1 at 303K. This value is consistent with that of previous reported results [3]. In summary, a relatively facile microfabrication process has been developed for characterizing the thermoelectrical properties of SiGe/Si MQWs materials. The processed thermalelectrical arrays show an expected TCR value as mathematical simulation.

Surface morphology and removal rates for dry- and wet-etched novel resonator materials: Part II. La 3Ga 5.5Nb 0.5O 14

Research on synthetic-grating SOI structure for simultaneous operation of 1310 and 1550 nanometer signal: A handy proposal of optical interconnect for photonic integrated circuits