Simulation of temperature and elastic fields and phase transitions in SOI structures formed by pulse heating

In this study, we fabricated thermopile infrared sensor with floating membrane structure. Floating membrane was formed by SOI(Silicon On Insulator) structure. In SOI structure, silicon dioxide layer between top silicon layer and bottom silicon substrate was etched by HF solution, then membrane was floated over substrate. After membrane was floated, thermopile pattern was formed on membrane. By insertion of SOI technology, we could obtain thermal isolation structure easily and passivation process for sensor pattern protection was not required during fabrication process. Then, the amplifier circuit for thermopile sensor was fabricated by using <TEX>$1.5{\mu}m$</TEX> CMOS process. The voltage gain of fabricated amplifier was about two hundred.

A high resolution IR microscope, especially designed for measuring localized joule heating effect in silicon devices, has been developed by combining a ZnS objective lens and a HgCdTe infrared detector. This microscope has achieved the practical spatial resolution of 10 mu m and practical temperature resolution of 0.24 K. With this IR microscope, the joule heating effect in poly-Si (polycrystalline silicon) thin film resistors formed on SiO/sub 2/ thin layer has been measured, simulating SOI (silicon on insulator) structures. A significant temperature rise was observed in this device structure, because of the low thermal conductivity of the SiO/sub 2/ layer, suggesting the possibility of new reliability problems caused by the joule heating effect in SOI structures. >

Effect of high temperature - pressure on SOI structure

The current-voltage characteristics and the carrier-transport mechanism of the Er-silicide (ErSi1.7) Schottky contacts to strained-silicon-on-insulator (sSOI) and silicon-on-insulator (SOI) were investigated. Barrier heights of 0.74 eV and 0.82 eV were obtained for the sSOI and SOI structures, respectively. The barrier height of the sSOI structure was observed to be lower than that of the SoI structure despite the formation of a Schottky contact using the same metal silicide. The sSOI structure exhibited better rectification and higher current level than the SOI structure, which could be associated with a reduction in the band gap of Si caused by strain. The generation-recombination mechanism was found to be dominant in the forward bias for both structures. Carrier generation along with the Poole-Frenkel mechanism dominated the reverse-biased current in the SOI structure. The saturation tendency of the reverse leakage current in the sSOI structure could be attributed to strain-induced defects at the interface in non-lattice-matched structures.

The IR properties in SOI wafers formed by oxygen implantation into silicon

The work is devoted to calculation of static elastic and thermo-elastic fields in a homogeneous medium with a finite number of isolated heterogeneous inclusions. Firstly, the problem is reduced to the solution of inte-gral equations for strain and stress fields in the medium with inclusions. Then, Gaussian approximating func-tions are used for discretization of these equations. For such functions, the elements of the matrix of the dis-cretized problem are calculated in explicit analytical forms. The method is mesh free, and only the coordi-nates of the approximating nodes are the geometrical information required in the method. If such nodes compose a regular grid, the matrix of the discretized problem obtains the Toeplitz properties. By the calcula-tion of matrix-vector products with such matrices, the Fast Fourier Transform technique may be used. The latter accelerates essentially the process of the iterative solution of the disretized problem. The results of calculations of elastic fields in 3D-medium with an isolated spherical heterogeneous inclusion are compared with exact solutions. Examples of the calculation of elastic and thermo-elastic fields in the medium with several inclusions are presented.

The effects of temperature and frequency dispersion on sound speed in bulk poly (vinyl alcohol) poly (N-isopropylacrylamide) hydrogels caused by the phase transition

By an improved Al2O3(100) growth on Si(100) using O2 gas instead of N2O gas, high-crystalline quality silicon on insulator (SOI) and multistacked SOI structures were successfully fabricated on a 2-inch Si(100) wafer by the ultrahigh-vacuum chemical vapor deposition (UHV-CVD) method. The surface morphology of the Si top layer of the fabricated SOI structure is better than that of the silicon on sapphire (SOS) structure grown by the UHV-CVD method. The transistor action was confirmed from the electrical properties of the MOSFET, and the field effect mobility of 748 cm2/V s was obtained. These results were similar to those obtained from bulk Si. This improved Si top layer of SOI and multistacked SOI structures is due to the improved surface morphology and crystalline quality of the Al2O3 layer grown on Si with O2 gas.

An SOI-DRAM test device was fabricated on thin-film SOI (Silicon On Insulator) structure with 0.5 /spl mu/m CMOS/SIMOX (Separation by IMplanted OXygen) technology. Field-shield isolation and polysilicon pad techniques were introduced for the specific problems to thin-film SOI devices such as the floating body effects and increase of parasitic source/drain resistance, respectively. Keeping the thin-film SOI from etching off during DRAM cell processing was especially cared by using high-selectivity ECR etching technology. The bit-line capacitance of the experimental SOI-DRAM is reduced by 25% and the /RAS access time is 30% faster compared with the equivalent Bulk-Si DRAM. Low voltage DRAM operation down to 2 V range is also observed. >

The generalized Replica Exchange Method (gREM) is extended into the isobaric-isothermal ensemble, and applied to simulate a vapor-liquid phase transition in Lennard-Jones fluids. Merging an optimally designed generalized ensemble sampling with replica exchange, gREM is particularly well suited for the effective simulation of first-order phase transitions characterized by "backbending" in the statistical temperature. While the metastable and unstable states in the vicinity of the first-order phase transition are masked by the enthalpy gap in temperature replica exchange method simulations, they are transformed into stable states through the parameterized effective sampling weights in gREM simulations, and join vapor and liquid phases with a succession of unimodal enthalpy distributions. The enhanced sampling across metastable and unstable states is achieved without the need to identify a "good" order parameter for biased sampling. We performed gREM simulations at various pressures below and near the critical pressure to examine the change in behavior of the vapor-liquid phase transition at different pressures. We observed a crossover from the first-order phase transition at low pressure, characterized by the backbending in the statistical temperature and the "kink" in the Gibbs free energy, to a continuous second-order phase transition near the critical pressure. The controlling mechanisms of nucleation and continuous phase transition are evident and the coexistence properties and phase diagram are found in agreement with literature results.

Binary GexS100-x glasses reveal a richness of elastic and chemical phase transitions driven by network topology. With increasing Ge content (x), well-defined rigidity at xc(1) = 19.3(5)% and a stress transition at xc(2) = 24.9(5)% are observed in Raman scattering. In modulated DSC measurements, the nonreversing enthalpy of relaxation at Tg reveals a square-well-like minimum (reversibility window) with window walls that coincide with the two elastic phase transitions. Molar volumes show a trapezoidal-like minimum (volumetric window) with edges that nearly coincide with the reversibility window. These optical, thermal, and volumetric results are consistent with an isostatically rigid elastic phase (intermediate phase, IP) present between the rigidity (xc(1)) and stress (xc(2)) transitions. Complex Cp measurements show melt fragility index, m(x) to also show a global minimum in the reversibility window with m < 20, underscoring that melt dynamics encode the elastic behavior of the glass formed at Tg. The strong nature of melts formed in the IP has an important practical consequence; they lead to slow homogenization (over days not hours) of nonstoichiometric Ge-S batch compositions reacted at high temperatures. Homogenization of chalcogenide melts/glasses over a scale of a few micrometers is a prerequisite to observe the intrinsic physical properties of these materials.

Research on synthetic-grating SOI structure for simultaneous operation of 1310 and 1550 nanometer signal: A handy proposal of optical interconnect for photonic integrated circuits

Selective buried oxide (SELBOX) Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) structure can be used to reduce the kink effect and self‐heating problems associated with the silicon on insulator (SOI) MOSFET devices while maintaining the advantages of bulk MOSFET. In this paper, static power dissipation of SELBOX structure is investigated and compared with SOI and bulk structures. Various MOSFET structures are simulated and evaluated in terms of their static power dissipation. Only results from 90‐nm Complementary Metal Oxide Semiconductor (CMOS) technology devices are included in this paper. Simulation results using the Silvaco TCAD show that static power dissipation in SELBOX CMOS is similar to that of SOI devices but lower than that of bulk CMOS. Hence, SELBOX structure is found to produce relatively low‐static power dissipation while maintaining high operating speed and reducing self‐heating and kink effect. A mathematical model to describe the static power dissipation in the subthreshold region is also included. Statistical analysis show that the model and fabrication simulation results agree with P &lt; .05 and correlation coefficient of 0.95.

The fabrication of freestanding SiC microstructures on Silicon-On-Insulator (SOI) and semi-insulating Silicon substrates is reported. SiC layers were grown on SOI and semi-insulating Si by chemical vapour deposition (CVD) and to avoid the instability currently obtained in SOI structures, the growth process parameters have been optimized. Isotropic wet chemical etching of the Si sacrificial layer released the electrostatic SiC microstructures patterned by dry etching. Moreover a new concept for reducing the gap between resonators and electrodes by the uses of bistable mobile electrodes is introduced.

ABSTRACTThis paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.