250 V Thin-Layer SOI Technology With Field pLDMOS for High-Voltage Switching IC

Analysis of the breakdown voltage in SOI and SOS technologies

In 0.5Ga 0.5P/In 0.22Ga 0.78As pseudomorphic high electron mobility transistors with an oxidized GaAs gate for improved breakdown voltage characteristics

This work demonstrates the performance comparison of ultrathin fully depleted (FD) silicon on insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) with various structures. The current drivability and immunity to the short channel effect are analyzed for FD-SOI n-channel MOSFETs (nMOSFETs) with various SOI layer thickness and SOI layer dopant concentrations based on the device simulation study. The SOI layer dopant concentrations are widely varied from conventional inversion-mode MOSFET, undoped-mode (intrinsic-mode) to the accumulation-mode MOSFET, where the accumulation-mode MOSFETs has the same dopant type in SOI layer as those of the source and the drain regions. The results suggest that the short channel effect immunity becomes comparable among various SOI layer dopant concentrations when SOI layer thickness is less than 10 nm. The current drivability is higher in the order of accumulation-, intrinsic-, and inversion-mode MOSFETs, and the mechanism of the current drivability increase is explained. In addition, accumulation-mode MOSFETs with polycrystalline silicon (poly-Si) gate electrode can maintain their high current drivability even for short channel generation because the gate capacitance decrease due to the poly-Si depletion effect does not arise. Thus, accumulation-mode MOSFETs can maximize the performance of the ultrathin FD-SOI MOSFETs.

By utilizing a lumped-multilayer-based method, we have studied the thermal behavior of a generalized rectangular macro with an extremely high power density of 2500 W/cm/sup 2/ on a microprocessor chip of average power density 40 W/cm/sup 2/. We consider both conventional bulk Si CMOS technology and silicon on insulator (SOI) CMOS. Practical features, including the presence of realistic packaging and interconnect structures are thoroughly analyzed. We found that the worst case temperature rise for such a hotspot is about 11% (/spl sim/7/spl deg/C) above the global chip temperature rise (/spl sim/80/spl deg/C) for 2500 W/cm/sup 2/ power density in SOI technology. As a result of the presence of buried oxide, the thermal behavior of a 15/spl times/300 /spl mu/m/sup 2/ macro in bulk technology is significantly different from SOI technology. It is also found that the existence of the interconnect layers and a solder ball optimally positioned right above the heated macro enables the heat flow to spread horizontally above the macro before eventually being dissipated downwardly toward the heat sink, thus decreasing the peak temperature rise of the macro in the device plane.

In this paper, the noise properties of transistors on 90 nm silicon on insulator (SOI) and bulk CMOS technologies are investigated. At 20 GHz, the SOI and bulk devices have minimum noise figures of 1 dB and 2.3 dB, respectively, demonstrating the superior performance of the SOI technology. The corresponding maximum available gain is 13 dB and 12 dB, respectively. For the first time, the drain and gate noise coefficients of shortchannel SOI devices are extracted yielding values of 2.15 and 1.7, respectively. Theoretical aspects are discussed to identify the main noise sources and to gain insights for optimizations. Furthermore, examples of analog monolithic integrated circuits fabricated on SOI technology are presented. Measured results are a noise figure of 4 dB for a low noise amplifier (LNA) at 40 GHz, a single side band noise figure of 9 dB for a passive mixer at 40 GHz and a phase noise of -90 dBc at 1 MHz offset for an voltage controlled oscillator (VCO) at 60 GHz. To the knowledge of the authors, these are the best noise performances achieved to date for CMOS based transistors and circuits at millimeter wave frequencies.

Recent developments in high-voltage devices have made it feasible to realize monolithic power integrated circuits that combine high voltage devices with control, level shifter and logic function on a single chip. One of the important uses of such circuits is to assemble bridge circuits, which are needed whenever waveforms of arbitrary shape and frequency have to be synthesized. Typical examples are electronic ballasts and motor drives. In such circuits the source of the upper of the two switches, the high-side transistor, has to float above ground potential. In this work we have studied, both theoretically and experimentally, the behavior of junction-isolated (JI) and silicon-on-insulator (SOI) devices in applications involving the source-follower configuration at voltages up to 700 V. We find that the SO1 devices exhibit significantly lower on-resistance under source-high conditions than do JI devices, and that this effect is especially pronounced at high source bias voltages. The devices used in this study were LDMOS transistors, with off-state breakdown voltages of 500-700V (Fig. 1). Both types of devices were designed according to the RESURF principle in order to maximize the breakdown voltage [l, 21. Measurements of the on-state Id - Vh characteristic of the JI transistor in common-source and source-high configurations indicate that, in the latter case, the difference between the substrate and source potentials causes the drift region of the LDMOS transistor to become depleted, resulting in an increase of the on-resistance. In the case of the the SO1 device, however, an inversion layer forms at the buried oxide-SO1 layer interface. Once strong inversion is established, the width of the depletion region does not increase with further increase in the substrate potential, so that the remainder of the SO1 layer remains undepleted. Consequently, relatively little change occurs in the on-resistance of the SO1 device after the initial onset of the inversion layer. As a consequence of the RESURF principle which imposes conditions on the drift region charge, the specific on-resistances of the JI and SO1 devices in common-source configuration are comparable. However, as the source potential increases, the SO1 on-resistance increases slightly and saturates to a constant value, while the on-resistance of the JI device increases much more drastically (Fig. 2). This effect in JI devices can be alleviated to some extent by design modifications, such as the use of a lightly-doped substrate, a thicker epitaxial layer or inclusion of additional charge-compensating regions [3]. However, the effectiveness of such modifications at very high voltages is limited. For this reason, the source-follower operation becomes more difficult to realize in very-high- breakdown-voltage JI devices. This behavior has important implications on the ability to integrate high-voltage source-follower devices in power integrated circuits. The substantial increase in the on-resistance of the JI transistor would necessitate a correspondingly large increase in the device area, making the integration impractical. Such a limitation does not exist in the SO1 technology, which is thus more suitable for integrating multiple power devices on a single chip.

Monolithic active pixel detectors fabricated in SOI (silicon on insulator) technology are novel sensors of ionizing radiation which exploit SOI substrates for the integration of readout electronics with a pixel detector. The fully-depleted sensing diode is manufactured under the SOI buried oxide (BOX) in the volume of the `handle wafer', while readout circuitry occupies the upper silicon SOI `device layer'. However, the initial prototypes suffered from significant leakage currents and early breakdown of pixel diodes. These effects limited the production yield. Moreover, the p-wells within the device layer extended to the interface with the BOX, which caused some local potential wells below the BOX at the top of the depleted sensor area. As a result, the effective charge collection efficiency was significantly decreased. This paper describes a solution for these problems employing a thicker 4 ¿m SOI device layer. The use of this detector structure has increased the effective charge collection efficiency to over 99%.

The sensitivity to heavy ions of nonhardened 0.25-/spl mu/m partially depleted (PD) silicon on insulator (SOI) and bulk technologies is studied with experiments, device, and circuit simulations. Comparable threshold linear energy transfer (LET) are found for both technologies. Nevertheless, SOI saturated cross section is much lower than bulk one. For nonhardened technologies, SOI is then less sensitive than bulk to heavy ions.

A smart power transistor for high voltage inverter applications

This paper describes the fabrication and the performance analysis of 65 nm PMOS using Silicon‐on‐Insulator (SOI) technology. As the technology evolved towards minimizing the scaling size, the scaling activity has it own limitations. The Silicon‐on‐Insulator (SOI) is the primary method used to overcome the scaling limitation. In this paper, the 65 nm PMOS device with 0.4 μm thickness of Silicon‐on‐Insulator (SOI) Technology was fabricated and the performance of the devices was analyzed by focusing on the electrical characteristics of Id‐Vd and Id‐Vg curves for bulk PMOS and the one with SOI technology. The fabrication process simulation and electrical characteristic was simulated using SILVACO TCAD ATHENA and ATLAS simulator. A very promising results were obtained, the device with SOI technology shows improvement in drain saturation current of Idsat = −269 uA/um from −257 uA/um of bulk PMOS (with increment of 4.7%) and the SOI device exhibits lower threshold voltage of pVth(SOI) = −0.2165 V compared to pVt...

This technical paper investigates the electrical analysis in sub 90 nm of PMOS. The investigation was carried out by using two different methods which is PMOS with strained silicon and Silicon‐on‐Insulator (SOI) technology. Strained silicon engineering has become a key innovation to enhance device on current. Recently, SOI technology has been widely accepted for use in mainstream high performance logic applications due to some advantageous offered over the bulk silicon. The performance of the devices is analyzed by focusing on the electrical characteristics of Id−Vd and Id−Vg curves for three different structures. Firstly, PMOS with strained silicon of Si3N4 capping layer covering the gate area and secondly the device with and without SOI technology. The fabrication process simulation was simulated by using SILVACO TCAD ATHENA simulator and the electrical characteristic was simulated by SILVACO TCAD ATLAS simulator to obtain Id−Vd and Id−Vg curves. A fruitful and knowledgeable results were reported from this paper, it could be seen that high tensile strain introduced to the device causing the drain current to decreased from Id(bulk) = −400 uA/um of bulk to Id(Strain) = −310 uA/um which is about 25% of decrement. Since the drain current decreased, the carrier mobility and the performance also decreased proportional to drain current. However when SOI technology is applied to the PMOS device, the drain current was increased up to Id(SOI) = −431 uA/um over the bulk, the increment of about 9.25% reported. A higher Id−Vg curve and lower threshold of about pVth(SOI) = −0.2178 V also reported from this paper which tells that the device with SOI technology exhibits low power consumption device and fast switching which in turns contribute to a faster performance.

A high-side thin-layer silicon-on-insulator (SOI) pLDMOS is proposed, adopting field implant (FI) and multiple field plate (MFP) technologies. The breakdown mechanisms of back gate (BG) turn-on, surface channel punch-through, and vertical and lateral avalanche breakdown are investigated by setting up analytical models, simulating related parameters and verifying experimentally. The device structure is optimized based on the above research. The shallow junction achieved through FI technology attenuates the BG effect, the optimized channel length eliminates the surface channel punch-through, the advised thickness of the buried oxide dispels the vertical avalanche breakdown, and the MFP technology avoids premature lateral avalanche breakdown by modulating the electric field distribution. Finally, for the first time, a 300 V high-side pLDMOS is experimentally realized on a 1.5 μm thick thin-layer SOI.

We have grown thin strain-relaxed SiGe buffer layers on silicon-on-insulator (SOI) substrates with pure-edge dislocation network at the SiGe/SOI interface. Dislocation morphology and crystalline mosaicity of the SiGe layers have been analyzed by X-ray diffraction two-dimensional reciprocal space mapping and transmission electron microscopy. It was found that dislocation propagation at the SiGe/SOI interface and resultant crystalline mosaicity of the SiGe layer are critically dependent on the thickness of SOI layer. Image force exerted on the dislocations accounts for this SOI thickness dependence.

Novel SOI (Silicon On Insulator) model parameter extraction methodology based on the concept of SHE (Self-Heating Effect) free device modeling, is proposed and demonstrated for a 0.18 /spl mu/m PD (Partially Depleted) SOI technology. In this methodology, prior to SPICE parameter extraction, the device thermal resistances are measured and the current loss due to SHE is added back analytically to DC I-V data. Therefore, the parameters are free from SHE. DC, AC, and transient simulation results using this technology show good agreement with measurement data.

In silicon-on-insulator (SOI) technology, devices are dielectrically insulated from one another—usually by silicon dioxide. Unlike in conventional silicon devices, there is no direct contact between a transistor and the silicon substrate. The advantages of this type of isolation are many: reduced parasitic capacitances and reduced crosstalk between devices, improved current drive, subthreshold characteristics, and current gain. Silicon-on-insulator devices have been and are being used in several niche-market applications such as hightemperature and radiation-hard integrated circuits. However most importantly, SOI technology seems perfectly adapted to the needs of low-voltage, low-power (LVLP) electronic circuits. Because of the growing market for portable systems, LVLP technology is bound to soon become one of the drivers of the microelectronics industry, and SOI is likely to be part of it. Moreover major companies such as IBM, Sharp, Motorola, and Peregrine have announced upcoming lowpower and high-frequency lines of SOI products. The goal of this article is to introduce the reader to the basics of SOI device physics and the integrated-circuit applications of SOI.