Characterization of SOI monolithic detector system

Silicon-on-insulator (SoI) monolithic active pixel sensors have been developing fast in recent years. An SoI sensors use a thin low-resistivity upper Si layer for circuit implementation, and a high-resistivity bottom wafer as a sensor, sandwiching a buried oxide layer. These devices can be made very thin, fully depleted, avoiding bump bonding. In addition, they have fine pitch and low capacitance. An SoI pixel is a very attractive technology due to its inherent advantages. An SoI pixel process for monolithic radiation detectors is developed mainly based on Lapis Semiconductor Co. Ltd. 0.2-μm SoI FD-CMOS technology. The multilateral developments for both fundamental properties and dedicated application are progressing simultaneously. There have been many research projects on high-energy physics, space experiments, synchrotron radiation and industrial scan, and so on. Difficulties are unavoidable in the R&D process and many of them are solved by introducing new techniques, process/structure modifications, such as buried p-well, double-SoI, and 3-D vertical integration. This paper provides a review of the SoI sensor development: the theory; features; key issues; process; research; and applications.

ALICE (A Large Ion Collider Experiment) is the heavy-ion experiment at the Large Hadron Collider (LHC) at CERN. As an important part of its upgrade plans, the ALICE experiment will schedule the installation of a new Inner Tracking System (ITS) during the Long Shutdown 2 (LS2) of the LHC. The new ITS layout will consist of seven concentric layers, $\approx$ 12.5 Gigapixel camera covering about 10m$^2$ with Monolithic Active Pixel Sensors (MAPS). This choice of technology has been guided by the tight requirements on the material budget of 0.3$\%$ X/X$_0$ per layer for the three innermost layers and backed by the significant progress in the field of MAPS in recent years. The technology initially chosen for the ITS upgrade is the TowerJazz 180 nm CMOS Technology. It offers a standard epitaxial layer of 15 - 18 $\mu$m with a resistivity between 1 and 5 k$\Omega$~cm$^{-1}$ and a gate oxide thickness below 4 nm, thus being more robust to Total Ionizing Dose (TID). The main subject of this thesis is to implement a novel digital pixel readout architecture for MAPS. This thesis aims to study this novel readout architecture as an alternative to the rolling-shutter readout. However, this must be investigated through the study of several chip readout architectures during the R$\&$D phase. Another objective of this thesis is the study and characterization of TowerJazz, if it meets the Non-Ionizing Energy Loss (NIEL) and Single Event Effects (SEE) of the ALICE ITS upgrade program. Other goals of this thesis are: Implementation of the top-down flow for this CMOS process and the design of multiple readouts for different prototypes up to the assembly of a full-scale prototype. Characterization of the radiation hardness and SEE of the chips submitted to fabrication. Characterization of full custom designs using analog simulations and the generation of digital models for the simulation chain needed for the verification process. \item Implementation and study of different digital readouts to meet the ITS upgrade program in integration time, pixel size and power consumption, from the conceptual idea, production and fabrication phase. SChapter 1 is a brief overview of CERN, the LHC and the detectors complex. The ALICE ITS will be explained, focusing on the ITS upgrade in terms of detector needs and design constraints. Chapter 2 explains the properties of silicon detectors and the detector material and the principles of operation for MAPS. Chapters 3 and 4 describe the ALPIDE prototypes and their readout based on MAPS; this forms the central part of this work, including the multiple families of pixel detectors fabricated in order to reach the final design for the ITS. The ALPIDE3/pALPIDE3B chip, the latest MAPS chip designed, will be explained in detail, as well focusing in the matrix digital readout. In chapter 5 the noise measurements and its characterization are presented including a brief summary of detector response to irradiation with soft X-rays, sources and particle beams. on the ITS upgrade in terms of detector needs and design constraints. Chapter 2 explains the properties of silicon detectors and the detector material and the principles of operation for MAPS. Chapters 3 and 4 describe the ALPIDE prototypes and their readout based on MAPS; this forms the central part of this work, including the multiple families of pixel detectors fabricated in order to reach the final design for the ITS. The ALPIDE3/pALPIDE3B chip, the latest MAPS chip designed, will be explained in detail, as well focusing in the matrix digital readout. In chapter 5 the noise measurements and its characterization are presented including a brief summary of detector response to irradiation with soft X-rays, sources and particle beams.

ID: 139 Monte Carlo simulations for imaging in proton therapy

Monolithic active pixel detectors fabricated in SOI (silicon on insulator) technology are novel sensors of ionizing radiation which exploit SOI substrates for the integration of readout electronics with a pixel detector. The fully-depleted sensing diode is manufactured under the SOI buried oxide (BOX) in the volume of the `handle wafer', while readout circuitry occupies the upper silicon SOI `device layer'. However, the initial prototypes suffered from significant leakage currents and early breakdown of pixel diodes. These effects limited the production yield. Moreover, the p-wells within the device layer extended to the interface with the BOX, which caused some local potential wells below the BOX at the top of the depleted sensor area. As a result, the effective charge collection efficiency was significantly decreased. This paper describes a solution for these problems employing a thicker 4 ¿m SOI device layer. The use of this detector structure has increased the effective charge collection efficiency to over 99%.

The features of the 180nm TowerJazz1 CMOS technology allow for the first time the use of CMOS Monolithic Active Pixel Sensors (MAPS) under the harsh operational conditions of the LHC experiments. The stringent requirements of the ALICE Inner Tracking System (ITS) in terms of material budget, radiation hardness, readout speed and a low power consumption have thus lead to the choice of MAPS as baseline technology option for the recently approved upgrade of the ITS and are the key drivers for R&D efforts on basic transistor and Explorer and MIMOSA pixel sensor prototypes produced in TowerJazz technology. Though the radiation loads expected for the ITS are below those of ATLAS and CMS, it is however necessary to assess the radiation hardness for ITS MAPS prototypes. Total Ionizing Dose (TID) radiation hardness has been established for basic transistor structures using a 60keV X-ray machine. The main operational characteristics and detection properties such as noise, charge collection efficiency and signal over noise ratio of Explorer-0 and MIMOSA32 and MIMOSA34 pixel sensor prototypes have been studied using X-rays (55Fe) and test beams at CERN and DESY before and after Non Ionizing Energy Loss (NIEL) and TID irradiation. In this paper the results of these R&D activities will be presented and discussed.

This technical paper investigates the electrical analysis in sub 90 nm of PMOS. The investigation was carried out by using two different methods which is PMOS with strained silicon and Silicon‐on‐Insulator (SOI) technology. Strained silicon engineering has become a key innovation to enhance device on current. Recently, SOI technology has been widely accepted for use in mainstream high performance logic applications due to some advantageous offered over the bulk silicon. The performance of the devices is analyzed by focusing on the electrical characteristics of Id−Vd and Id−Vg curves for three different structures. Firstly, PMOS with strained silicon of Si3N4 capping layer covering the gate area and secondly the device with and without SOI technology. The fabrication process simulation was simulated by using SILVACO TCAD ATHENA simulator and the electrical characteristic was simulated by SILVACO TCAD ATLAS simulator to obtain Id−Vd and Id−Vg curves. A fruitful and knowledgeable results were reported from this paper, it could be seen that high tensile strain introduced to the device causing the drain current to decreased from Id(bulk) = −400 uA/um of bulk to Id(Strain) = −310 uA/um which is about 25% of decrement. Since the drain current decreased, the carrier mobility and the performance also decreased proportional to drain current. However when SOI technology is applied to the PMOS device, the drain current was increased up to Id(SOI) = −431 uA/um over the bulk, the increment of about 9.25% reported. A higher Id−Vg curve and lower threshold of about pVth(SOI) = −0.2178 V also reported from this paper which tells that the device with SOI technology exhibits low power consumption device and fast switching which in turns contribute to a faster performance.

Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

This paper describes the fabrication and the performance analysis of 65 nm PMOS using Silicon‐on‐Insulator (SOI) technology. As the technology evolved towards minimizing the scaling size, the scaling activity has it own limitations. The Silicon‐on‐Insulator (SOI) is the primary method used to overcome the scaling limitation. In this paper, the 65 nm PMOS device with 0.4 μm thickness of Silicon‐on‐Insulator (SOI) Technology was fabricated and the performance of the devices was analyzed by focusing on the electrical characteristics of Id‐Vd and Id‐Vg curves for bulk PMOS and the one with SOI technology. The fabrication process simulation and electrical characteristic was simulated using SILVACO TCAD ATHENA and ATLAS simulator. A very promising results were obtained, the device with SOI technology shows improvement in drain saturation current of Idsat = −269 uA/um from −257 uA/um of bulk PMOS (with increment of 4.7%) and the SOI device exhibits lower threshold voltage of pVth(SOI) = −0.2165 V compared to pVt...

A 250 V thin-layer SOI technology based on a 1.5-μm-thick SOI layer is developed for high-voltage (HV) switching IC. HV thin-layer silicon on insulator (SOI) field p-channel LDMOS (pLDMOS) with thick gate oxide layer, SOI RESURF n-channel LDMOS (nLDMOS) with thin gate oxide layer, and low-voltage CMOS are monolithically integrated. Compared with the conventional SOI technology integrating field pLDMOS, the thickness of SOI layer is reduced from above 5 μm to only 1.5 μm. The field implant (FI) technology is adopted to eliminate channel discontinuity underneath the bird's beak and achieve shallow junction depth to avoid back gate (BG) punchthrough breakdown for the field pLDMOS. A BG punchthrough model is presented with simulation results. The field pLDMOS with breakdown voltage (BV) of -329 V and RESURF nLDMOS with BV of 338 V are experimentally realized. A 250 V switching IC using the field pLDMOS and RESURF nLDMOS as the level-shift and the output stage is also presented based on the developed thin-layer SOI technology.

By utilizing a lumped-multilayer-based method, we have studied the thermal behavior of a generalized rectangular macro with an extremely high power density of 2500 W/cm/sup 2/ on a microprocessor chip of average power density 40 W/cm/sup 2/. We consider both conventional bulk Si CMOS technology and silicon on insulator (SOI) CMOS. Practical features, including the presence of realistic packaging and interconnect structures are thoroughly analyzed. We found that the worst case temperature rise for such a hotspot is about 11% (/spl sim/7/spl deg/C) above the global chip temperature rise (/spl sim/80/spl deg/C) for 2500 W/cm/sup 2/ power density in SOI technology. As a result of the presence of buried oxide, the thermal behavior of a 15/spl times/300 /spl mu/m/sup 2/ macro in bulk technology is significantly different from SOI technology. It is also found that the existence of the interconnect layers and a solder ball optimally positioned right above the heated macro enables the heat flow to spread horizontally above the macro before eventually being dissipated downwardly toward the heat sink, thus decreasing the peak temperature rise of the macro in the device plane.

Development of a triple well CMOS MAPS device with in-pixel signal processing and sparsified readout capabilities

The SiD detector concept capitalizes on high granularity in its tracker and calorimeter to achieve the momentum resolution and particle flow calorimetry physics goals in a compact design. The collaboration has had a long interest in the potential for improved granularity in both the tracker and ECal with an application of monolithic active pixel sensors (MAPS) and a study of MAPS in the SiD ECal was described in the ILC TDR. Work is progressing on the MAPS application in an upgraded SiD design with a prototyping design effort for a common SiD tracker/ECal design based on stitched reticules to achieve 10 × 10 cm2 sensors with 25 × 100 micron2 pixels. Application of large area MAPS in these systems would limit delicate and expensive bump-bonding, provide possibilities for better timing, and should be significantly cheaper than the TDR concept due to being a more conventional CMOS foundry process. The small pixels significantly improve shower separation. Recent simulation studies confirm previous performance projections, indicating electromagnetic energy resolution based on digital hit cluster counting provides better performance than the SiD TDR analog design based on 13 mm2 pixels. Furthermore, the two shower separation is excellent down to the millimeter scale. Geant4 simulation results demonstrate these expectations.

LePix—A high resistivity, fully depleted monolithic pixel detector

A novel monolithic active pixel detector in [formula omitted] triple well CMOS technology with pixel level analog processing

Performance of the Silicon-On-Insulator pixel sensor for X-ray astronomy, XRPIX6E, equipped with pinned depleted diode structure