Effective self-embedding watermarking scheme for image tampered detection and localization with recovery capability

Digital medical image has a potential to be manipulated by unauthorized persons due to advanced communication technology. Verifying integrity and authenticity have become important issues on the medical image. This paper proposed a self-embedding watermark using a spiral block mapping for tamper detection and restoration. The block-based coding with the size of 3×3 was applied to perform self-embedding watermark with two authentication bits and seven recovery bits. The authentication bits are obtained from a set of condition between sub-block and block image, and the parity bits of each sub-block. The authentication bits and the recovery bits are embedded in the least significant bits using the proposed spiral block mapping. The recovery bits are embedded into different sub-blocks based on a spiral block mapping. The watermarked images were tested under various tampered images such as blurred image, unsharp-masking, copy-move, mosaic, noise, removal, and sharpening. The experimental results show that the scheme achieved a PSNR value of about 51.29 dB and a SSIM value of about 0.994 on the watermarked image. The scheme showed tamper localization with accuracy of 93.8%. In addition, the proposed scheme does not require external information to perform recovery bits. The proposed scheme was able to recover the tampered image with a PSNR value of 40.45 dB and a SSIM value of 0.994.

With the development of depth data acquisition technologies, access to high-precision depth with more than 8-b depths has become much easier and determining how to efficiently represent and compress high-precision depth is essential for practical depth storage and transmission systems. In this paper, we propose a layered high-precision depth compression framework based on an 8-b image/video encoder to achieve efficient compression with low complexity. Within this framework, considering the characteristics of the high-precision depth, a depth map is partitioned into two layers: 1) the most significant bits (MSBs) layer and 2) the least significant bits (LSBs) layer. The MSBs layer provides rough depth value distribution, while the LSBs layer records the details of the depth value variation. For the MSBs layer, an error-controllable pixel domain encoding scheme is proposed to exploit the data correlation of the general depth information with sharp edges and to guarantee the data format of LSBs layer is 8 b after taking the quantization error from MSBs layer. For the LSBs layer, standard 8-b image/video codec is leveraged to perform the compression. The experimental results demonstrate that the proposed coding scheme can achieve real-time depth compression with satisfactory reconstruction quality. Moreover, the compressed depth data generated from this scheme can achieve better performance in view synthesis and gesture recognition applications compared with the conventional coding schemes because of the error control algorithm.

Based on the NEQR of quantum images, a new quantum gray-scale image watermarking scheme is proposed through Arnold scrambling and least significant bit (LSB) steganography. The sizes of the carrier image and the watermark image are assumed to be $$2n\times 2n$$ and $$n\times n$$ , respectively. Firstly, a classical $$n\times n$$ sized watermark image with 8-bit gray scale is expanded to a $$2n\times 2n$$ sized image with 2-bit gray scale. Secondly, through the module of PA-MOD N, the expanded watermark image is scrambled to a meaningless image by the Arnold transform. Then, the expanded scrambled image is embedded into the carrier image by the steganography method of LSB. Finally, the time complexity analysis is given. The simulation experiment results show that our quantum circuit has lower time complexity, and the proposed watermarking scheme is superior to others.

There is a huge resource of data available on the internet which one can access without realizing that the person is even authorized to access it or not. The hard work of the original resource person can easily be compromised. Digital watermarking is an answer to overcome this issue. This paper introduces a hybrid of LSB and DCT techniques, LSB(Least Significant Bit) and DCT(Discrete Cosine Transformation). The paper studies the two techniques along with the proposed technique and a comparison is drawn between the three based on MSE and PSNR values obtained. The introduced hybrid technique performs better in comparison to DCT and LSB. The MSE calculated was 64% better than LSB and 60% better than DCT resultantly PSNR is also observed to be better than LSB and DCT.

The confidential information is communicated through the open channel in a covert way by using steganography. In this paper we propose the Covariance based Steganography using Discrete Cosine Transform (CSDCT) algorithm. The Average Covariance of the Cover Image (ACCI) is computed and threshold ACCI value is fixed at 0.15. The cover image is segmented into 8*8 cells and the Least Significant Bit (LSBs) are replaced by Most Significant Bits (MSBs) of payload based on ACCI values. It is observed that the capacity, Peak Signal to Noise Ratio (PSNR) and security is better compared to the existing algorithm.

We have designed, fabricated and successfully tested digital error-correction circuits to improve the performance of superconductive flash analog-to-digital converters (ADCs). The comparators coding the most significant bits (MSBs) are the least sensitive to the input signal, and therefore have the most threshold errors due to jitter and threshold misplacement. These errors are completely eliminated by implementing an ADC architecture using two comparators per bit, and employing logic to encode bit N by looking back to the state of the (N-1) bit. In this way, all code transitions are derived from the least significant bit (LSB) comparators. The MSB comparators are used only to encode the LSB data.

22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

This paper explores the effectiveness of different knobs to dynamically trade energy consumption with output quality in approximate SRAMs for error-tolerant applications (such as video). Leveraging the different impact of errors on quality at most significant bit (MSB) and least significant bit (LSB) positions, energy savings higher than those provided by simple voltage scaling are enabled. Firstly, a comparison of two techniques, dual-VDD and LSB dropping, is carried out showing that the latter is preferable thanks to its intrinsic simplicity and more pronounced energy savings. Secondly, a selective Error Correction Code (ECC) technique which reuses the LSBs as check bits to protect MSBs is investigated. Measurements on a 28nm CMOS 32kb SRAM show that bit dropping and bit reuse achieve an energy reduction of up to 33% and 28%, compared to simple voltage scaling at iso-quality. When combined together, the two techniques achieve a better energy saving (40%) and a supply voltage reduction of about 100mV at iso-quality. Finally, guidelines to select the energy-optimal combination of the two techniques are provided for a given quality target.

This article presents a 25-Gb/s single-ended four-level pulse-amplitude modulation (PAM-4) receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory interfaces. The proposed PAM-4 decoding technique obviates the need for additional comparators and reference voltages that are required in conventional PAM-4 decoders. Similar to conventional non-return-to-zero (NRZ) receivers, the proposed PAM-4 receiver uses only one comparator by decoding the LSB through time-windowing the outputs of the comparator that is used to decide a most significant bit (MSB). Therefore, the additional power overhead from a power-hungry analog front-end (AFE) and high-speed clock buffers is minimized in the proposed PAM-4 receiver because it is proportional to the number of comparators. Accordingly, the proposed PAM-4 receiver can achieve superior energy efficiency. Furthermore, the elimination of the use of reference voltages reduces the hardware cost and design complexity. A prototype single-ended PAM-4 receiver was fabricated in a 28-nm CMOS technology. It occupies 0.008 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and consumes 0.34 pJ/bit at 25 Gb/s.

Steganography algorithms used to secure sensitive data on the Internet. It hides the secret data in the cover image and provides imperceptibility to the attacker. The least significant bit (LSB) is the most preferred data hiding technique in the steganography. In this technique, the least significant bit of the cover image pixel replaced with data bits. In the literature, the data hiding achieved without considering the human visual system (HVS) characteristics that degrade the visual quality of the image. In this paper, the optimized data hiding has done while considering the HVS characteristics. The colour image contains three planes known as the red–green–blue plane. The green plane is the most sensitive, and blue is less sensitive to the human eyes. Thus, in the proposed technique, the green plane used as a reference plane for data hiding in the red and blue planes. In the optimized data hiding technique, the secret data bits match with the cover pixel bits. If the bits match, then the corresponding optimal index determines, else data hiding done in the LSB bits of the cover pixel. After that, the optimal indexes hide in the cover image using a 2-bit LSB technique. In the proposed technique, image smooth and edge region characteristics explored before data hiding. There is a high correlation between the consecutive pixels in the smooth region and the minimum correlation on the edges. Thus, we have matched the secret data bits with the cover pixel bits in the smooth region and hide the optimal indexes on the edges. The experimental results performed on the standard dataset images downloaded from the USC-SIPI image database. The experimental results show that the proposed technique provides better visual quality as compared to the existing techniques.

As the extension of the least significant bits (LSB) steganographic algorithm, steganographic algorithm embedding in two least-significant bits (Two-LSBs for short) has some characteristics, such as visual imperceptibility, higher capacity and easy realization. A new steganalysis method is introduced to detect the existence of hidden message that are randomly embedded in LSB and the second significant bits (second-LSBs)of image pixels. It is proposed based on investigating the statistical characters of image data in LSB and the second significant bits with hidden message. It can estimate embedding rate and length of hidden message. The experiments present detection effect with different thresholds and embedding rates, and show the detection method is effective that detection rate is up to 90% when embedded rate is more than 20%.

Interpolating, dual resistor ladder digital-to-analog converters (DACs) typically use the fine, least significant bit (LSB) ladder floating upon the static most significant bit (MSB) ladder. The usage of the LSB ladder incurs a penalty in dynamic performance due to the added output resistance and switch matrix parasitic capacitance. Current biasing of the LSB ladder addresses this issue by employing active circuitry. We propose an inverted ladder DAC, where an MSB ladder slides upon two static LSB ladders. While using no active components this scheme achieves lower output resistance and parasitic capacitance for a given power budget. We present a 0.35-mum, 3.3-V implementation consuming 22-muA current with output resistance of 40 kOmega and effective parasitic capacitance of 650 fF

A low jitter 50 Gb/s PAM4 optical receiver in 130 nm SiGe BiCMOS

For higher order modulation, the reliabilities of the bits Gray-mapped onto the modulated symbol vary from the most significant bits (MSBs) to the least significant bits (LSBs). This paper introduces one constellation rearrangement method for SISO (Single-Input Single Output) system. For MIMO (Multiple-Input Multiple Output) system, the constellation rearrangement works also for lower order modulation by the construction of spatial signal. One constellation remapping method for MIMO system is also introduced in the paper. The simulation results show the performance gain for the SISO constellation remapping method.

This paper presents three new attacks on the RSA cryptosystem. The first two attacks work when k RSA public keys (N i ,e i ) are such that there exist k relations of the shape e i x − y i φ(N i ) = z i or of the shape e i x i − yφ(N i ) = z i where N i = p i q i , φ(N i ) = (p i − 1)(q i − 1) and the parameters x, x i , y, y i , z i are suitably small in terms of the prime factors of the moduli. We show that our attacks enable us to simultaneously factor the k RSA moduli N i . The third attack works when the prime factors p and q of the modulus N = pq share an amount of their least significant bits (LSBs) in the presence of two decryption exponents d 1 and d 2 sharing an amount of their most significant bits (MSBs). The three attacks improve the bounds of some former attacks that make RSA insecure.