Efficient discovery of regular stride patterns in irregular programs and its use in compiler prefetching

Data dependencies have become one of the main bottlenecks of current superscalar processors. Data speculation is gaining popularity as a mechanism to avoid the ordering imposed by data dependencies. Loads and stores are very good candidates for data speculation since their effective address has a regular behavior and then, they are highly predictable. In this paper we propose a mechanism called Address Prediction and Data Prefetching that allows load instructions to obtain their data at the decode stage. Besides, the effective address of load and store instructions is also predicted. These instructions and those dependent on them are speculatively executed. The technique has been evaluated for an out-of-order processor with a realistic configuration. The performance gain is about 19% in average and it is much higher for some benchmarks (up to 35%).

GPGPUs are predominantly being used as accelerators for general purpose data parallel applications. Most GPU applications are likely to exhibit regular memory access patterns. It has been observed that warps within a thread block show striding behavior in their memory accesses corresponding to the same load instruction. However, determination of this inter warp stride at thread block boundaries is not trivial. We observed that thread blocks along different dimensions have different stride values. Leveraging this observation, we characterize the relationship between memory address references of warps from different thread blocks. Based on this relationship, we propose a multidimensional grid aware address predictor that takes the advantage of SM level concurrency to correctly predict the memory address references for future thread blocks well in advance. Our technique provides a cooperative approach where information once learned is shared with all the SMs. When compared with the CTA-aware technique, our predictor enhances average prediction coverage by 36% while showing almost similar prediction accuracy.

Recent application studies have shown that many irregular applications have a generalized data parallelism that manifests itself as iterative computations over worklists of different kinds. In general, there are complex dependencies between iterations. These dependencies cannot be elucidated statically because they depend on the inputs to the program; thus, optimistic parallel execution is the only tractable approach to parallelizing these applications.We have built a system called Galois that supports this style of parallel execution. Its main features are (i) set iterators for expressing worklist-based data parallelism, and (ii) a runtime system that performs optimistic parallelization of these iterators, detecting conflicts and rolling back computations as needed.Our work builds on the Galois system, and it addresses the problem of scheduling iterations of set iterators on multiple cores. The policy used by the base Galois system is to assign an iteration to a core whenever it needs work to do, but we show in this paper that this policy is not optimal for many applications. We also argue that OpenMP-style DO-ALL loop scheduling directives such as chunked and guided self-scheduling are too simplistic for irregular programs. These difficulties led us to develop a general scheduling framework for irregular problems; OpenMP-style scheduling strategies are special cases of this general approach. We also provide hooks into our framework, allowing the programmer to leverage application knowledge to further tune a schedule for a particular application.To evaluate this framework, we implemented it as an extension of the Galois system. We then tested the system using five real-world, irregular, data-parallel applications. Our results show that (i) the optimal scheduling policy can be different for different applications and often leverages application-specific knowledge and (ii) implementing these schedules in the Galois system is relatively straightforward.

This paper presents the design and implementation of a pipelined 9-bit RISC Processor. The various blocks include the Fetch, Decode, Execute and Store result to implement 4 stage pipelining. Harvard Architecture is used which has distinct program memory space and data memory space. The only load and store is used to communicate with data memory. RISC using pipeline makes CPI as 1 and improves speed of execution. Verilog Language is used for coding purpose. The proposed architecture is then simulated using Modelsim. Reduced Instruction Set Computers (RISCs) are now use for all type of computational tasks. In the area of scientific computing, RISC workstations are being increasingly used for compute task such as DSP, DIP etc. RISC concepts help to achieve given levels of performance at significantly lower cost than other systems. Pipelined RISC improves speed and cost effectiveness over the ease of hardware description language programming and conservation of memory and RISC based designs will continue to grow in speed and ability. The main features of RISC processor are the instruction set can be hardwired to speed instruction execution. In the present work, the design of a 4-bit data width Reduced Instruction Set Computer (RISC) processor is presented. It has a complete instruction set, program and data memories, general purpose registers and a simple Arithmetical Logical Unit (ALU) for basic operations. In this design, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate load and store instructions access memory. The architecture supports 8 instructions to support Arithmetic, Logical, Shifting, and load -store operations. Verilog HDL has evolved as a standard hardware description language. A hardware descriptive language is a language used to describe a digital system. HDL's allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology- independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. More recently Verilog is used as an input for synthesis programs which will generate a gate-level description for the circuit. The simulator which is used for the language is Xilinx ISE and Modelsim. Verilog is capable of describing simple behaviour. Machine cycle instructions allow the processor to handle several instructions at the same time. The processor can work at a high clock frequency and thus yields higher speed. This paper is about design of a simple RISC processor and synthesizing it. The RISC architecture follows single-cycle instruction execution.

The design of software acceptance tests is as important to meeting contract goals as is the design of algorithms. This statement is particularly significant on fixed price contracts with tight schedules. An extreme instance of the demand placed on acceptance testing can be found in software projects wherein the only rigorous testing that required the Computer Program Configuration Item (CPCI) to exercise its repertoire of load and store instructions was the Formal Qualification Test (FQT). This paper is about such a project, the lessons learned from it, and provides an effective test approach for fixed price contracts. A word or two about the project is appropriate to establish the context that underscores the impact of the above assertion. Initially 30K (core words), 16-bit program instructions were to be developed within one year using a Varian 73 computer with 32K words of memory for a Command and Control application under a fixed price contract. A set of a priori conditions existed that tended to convey the impression that the inherent risks of this endeavor were reasonable. They were the “facts” that: Of the 30K (core words) to be written, 30% of this code already existed and would be used. Contractor standards would be allowed for documentation with limited use of Military Specifications No formal Design Reviews or audits would accompany the deliverable CPCI. Existent executive software would suffice. A competent and enthusiastic team was committed to the effort.

BackgroundSerial Analysis of Gene Expression (SAGE) is a DNA sequencing-based method for large-scale gene expression profiling that provides an alternative to microarray analysis. Most analyses of SAGE data aimed at identifying co-expressed genes have been accomplished using various versions of clustering approaches that often result in a number of false positives.Principal FindingsHere we explore the use of seriation, a statistical approach for ordering sets of objects based on their similarity, for large-scale expression pattern discovery in SAGE data. For this specific task we implement a seriation heuristic we term ‘progressive construction of contigs’ that constructs local chains of related elements by sequentially rearranging margins of the correlation matrix. We apply the heuristic to the analysis of simulated and experimental SAGE data and compare our results to those obtained with a clustering algorithm developed specifically for SAGE data. We show using simulations that the performance of seriation compares favorably to that of the clustering algorithm on noisy SAGE data.ConclusionsWe explore the use of a seriation approach for visualization-based pattern discovery in SAGE data. Using both simulations and experimental data, we demonstrate that seriation is able to identify groups of co-expressed genes more accurately than a clustering algorithm developed specifically for SAGE data. Our results suggest that seriation is a useful method for the analysis of gene expression data whose applicability should be further pursued.

Most studies of gender and computer science have been conducted (out of necessity) in gender-imbalanced environments. The findings often point to significant gender differences, leading the researchers to recommend strategies to meet these differences. One such recommendation is to adopt a female-friendly, contextual approach to curriculum development.1 In contrast, based on our recent and ongoing studies of undergraduate computer science (CS) students at Carnegie Mellon University, we hypothesize that in a more balanced environment, gender differences tend to dissolve. That is, the spectrum of interests, motivation, and personality types of men and of women becomes more alike than different. This leads us to be considerably more pragmatic in our recommendations for effective and positive change. Indeed, we believe that recommendations for curricular changes based on presumed gender differences can be misguided and may help reinforce, even perpetuate, stereotypes. Here, we describe some of the changes in the culture of computing as our undergraduate CS environment has become more balanced in three critical domains: gender, the mix of students and breadth of their interests, and the professional experiences afforded all students. Brief Background for the Evolving Culture In 1995, just 7percent (7 out of 96) of the entering freshmen CS majors at Carnegie Mellon were women. Since 1999, the percentage has increased nearly fivefold (on average, 45 out of 132), challenging trends across the country.2 Two major factors have contributed to the dramatic increase of women in CS at Carnegie Mellon: an outreach program for high school CS teachers that combined technical training with discussions of gender-gap issues and a broadened admissions policy (emphasizing diverse interests—along with high [End Page 110] achievement in mathematics and science—and de-emphasizing prior programming experience). To meet the needs of students with varying backgrounds, multiple entry routes were built into the first-year programming sequence.3 The subsequent creation of the proactive student organization Women@SCS has been catalytic in building an environment in which the new student body can flourish.4 Women@SCS explicitly provides crucial educational and professional experiences generally taken for granted by the majority in the community but typically unavailable for the minority participants.5 Many of these experiences are casual and often happen in social settings. For example, in an undergraduate CS program, male students often have the opportunity to discuss homework with roommates, with friends late at night, or over meals. Course and job information and recommendations are passed down from upperclassmen, from fraternity files, or from friends. Women students, being in the minority, do not have access to—in fact are often excluded from—these implicit and important advantages. As one proceeds into the professional world, similar phenomena occur. These key actions, and implications for other venues, are discussed further at the end of this paper. Our recent study, based on a set of interviews with seniors in the class of 2002, may be viewed to a limited degree as a follow-up to the intensive longitudinal studies of CS students at Carnegie Mellon carried out by Jane Margolis and Allan Fisher between 1995 and 1999.6 Their studies, funded by the Sloan Foundation and discussed in Unlocking the Clubhouse, were undertaken to help understand differences in male and female students' engagement (attachment, persistence, and detachment) with computer science, with a special focus on the gender imbalance in the field.7 A major goal was to devise and effect changes in recruitment, curriculum, pedagogy, and culture to encourage the broadest possible participation in the computing enterprise. Unlocking the Clubhouse paints a bleak picture for women in the undergraduate computer science program in the 1990s, one that still resonates with many CS programs across the nation. Margolis and Fisher note that for the most part, "women who were enthusiastic about computing find their confidence and interest extinguished in the college years."8 Consequently, many of the (few) women students who entered the...

Computer architects need a deep understanding of clients' workload in order to design and tune the architecture. Unfortunately, many important clients will not share their software to computer architects due to the proprietary or confidential nature of their software. One technique to mitigate this problem is producing synthetic traces (clone) that replicate the behavior of the original workloads. Unfortunately, today there is no universal cloning technique that can capture arbitrary memory access behavior of applications. Existing technique captures only temporal, but not spatial, locality. In order to study memory hierarchy organization beyond caches, such as including prefetchers and translation lookaside buffer (TLB), capturing only temporal locality is insufficient. In this paper, we propose a new memory access behavior cloning technique that captures both temporal and spatial locality. We abbreviate our scheme as Spatio-Temporal Memory (STM) cloning. We propose a new profiling method and statistics that capture stride patterns and transition probabilities. We show how the new statistics enable accurate clone generation that allow clones to be used in place of the original benchmarks for studying the L1/L2/TLB miss rates as we vary the L1 cache, L1 prefetcher, L2 cache, TLB, and page size configurations.

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption due to sub-threshold leakage current. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching can be used to turn off the memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places the memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy/performance trade-offs of these techniques and find that the dynamic threshold modulation achieves the best results for level-1 caches, improving the energy-delay product by 2% in a level-1 instruction cache and 7% in a level-1 data cache. Low-leakage transistors perform best for the level-2 cache as they reduce the static energy by up to 98% and improve the energy-delay product by more than a factor of 50.

Performance-enhancement techniques improve CPU speed at the cost of other valuable system resources such as power and energy. Software prefetching is one such technique, tolerating memory latency for high performance. In this article, we quantitatively study this technique's impact on system performance and power/energy consumption. First, we demonstrate that software prefetching achieves an average of 36% performance improvement with 8% additional energy consumption and 69% higher power consumption on six memory-intensive benchmarks. Then we combine software prefetching with a (unrealistic) static voltage scaling technique to show that this performance gain can be converted to an average of 48% energy saving. This suggests that it is promising to build low power systems with techniques traditionally known for performance enhancement. We thus propose a practical online profiling based dynamic voltage scaling (DVS) algorithm. The algorithm monitors system's performance and adapts the voltage level accordingly to save energy while maintaining the observed system performance. Our proposed online profiling DVS algorithm achieves 38% energy saving without any significant performance loss.

Performance-enhancement techniques improve CPU speed, but at higher cost to other valuable system resources such as power and energy. We study this trade-off using software prefetching as the system performance-enhancement technique. We first demonstrate software prefetching provides an average 36% performance boost with 8% more energy consumption and 69% higher power on six memory-intensive benchmarks. However, when we combine prefetching with a (unrealistic) static voltage scaling technique, the performance gain afforded by prefetching can be traded off for savings in power/energy consumption. In particular, we observe a 48% energy saving when we slow down the system with prefetching so as to match the performance of the system without prefetching. This suggests a promising approach to build low power systems by transforming traditional performance-enhancement techniques into low power methods. We thus propose a real time dynamic voltage scaling (DVS) algorithm that monitors a system's performance and adapts the voltage level accordingly while maintaining the observed system performance. Our dynamic DVS algorithm achieves a 38% energy saving without any performance loss on our benchmark suite.

In this paper the K-means (KM) and the Fuzzy C-means (FCM) algorithms were compared for their computing performance and clustering accuracy on different shaped cluster structures which are regularly and irregularly scattered in two dimensional space. While the accuracy of the KM with single pass was lower than those of the FCM, the KM with multiple starts showed nearly the same clustering accuracy with the FCM. Moreover the KM with multiple starts was extremely superior to the FCM in computing time in all datasets analyzed. Therefore, when well separated cluster structures spreading with regular patterns do exist in datasets the KM with multiple starts was recommended for cluster analysis because of its comparable accuracy and runtime performances.

Practice makes perfect

In recent studies [1-3], lots of hidden homology in DNA genome are not found by current comparative tools despite decades of research. Many scholars modeled the genome as a monotonous string, which limits and probably obstructs the discovery of some significant patterns. We propose an information-coding-based model called DNA As X (DAX) to improve the sensitivity in comparative genomic studies by integrating the principles and concepts of other disciplines including information coding theory and signal processing into genome analysis. The proposed DNA As X model uses character-analysis-free (CAF) techniques, where X is the intermediate for analysis that can be digit, code, signal, vector, tree, graph network and so on. It provides novel and comprehensive perspectives to further analyze and recognize the critical patterns hidden in DNA genomes. Comparing with traditional character-analysis-based (CAB) methods, DAX not only enriches the tools and the knowledge library of computational biology but also extends the domain from 1-D character string analysis to 2-D spatial/temporal domain. Furthermore, by applying the DAX model to the issue of exon prediction as an evaluation, we illustrate the insights behind this model. The experimental results show that the DAX methodology can improve the sensitivity in genome analysis by using the novel information-coding techniques.

Feature point matching aims to automatically establish point-to-point correspondences between two images acquired from the same scene but through two different viewpoints. This matching process is essential to many image processing and computer vision tasks, such as image registration, object detection and tracking, to name a few. However, the well-known SIFT feature descriptors together with the use of the nearest neighbor matching criterion oftentimes lead to many incorrect point-to-point correspondences. This would be incurred especially when the two images undergo a large viewpoint variation and/or contain a severely cluttered background. To improve the performance of feature point matching process, three contributions are made in this thesis: 1) mismatch removal; 2) common visual pattern discovery; and 3) feature histogram equalization (FHE). The first two are graph model-based approaches, and the last one is a novel technique on the enhancement of feature descriptors. More details are provided as follows. For certain image processing applications such as matching two images captured from disparate views, or the so-called wide-baseline image matching as demonstrated in this thesis, a sufficiently large number of point-to-point correspondences are needed in the first place. However, these corresponding pairs often contain mismatched ones. Consequently, the accuracy of the spatial transformation estimation between the two images under matching will be reduced to a certain degree. Therefore, how to identify and remove the mismatched corresponding pairs from the established ones is the main goal of our first contribution. For that, a bipartite graph model is exploited to the segmented image regions to establish all possible region-to-region correspondences. After that one-to-one region correspondences, called the coherent region pairs (CRPs), can be further identified by using the Hungarian method and the proposed region-to-region similarity measurement metric. The established CRPs will be utilized as the reference information in order to identify and remove those mismatched point-to-point correspondences. Extensive experimental results have demonstrated that our proposed mismatch removal method could reduce incorrect SIFT-based point-to-point correspondences for the application of wide-baseline image matching that normally requires a large targeted number of matching pairs. For the second contribution on common visual pattern discovery, the entire work still begins with the SIFT feature descriptors. However, the main objective is to yield the correct point-to-point matching pairs in the first place, while the actual number of such established matching pairs tends to be small. The key novelty of our approach lies in the use of the directed graph (or diagraph) model that has two link weights on each link, rather than one link weight inherited in the conventional graph model. The principle of pairwise spatial consistency is first exploited to generate the initial link weight for each link. Based on this link weight value, two relative link weights are then generated by considering the relativeness of neighboring vertices at each vertex of the link. For that, the n-ranking process and a novel link weight enhancement technique are proposed. Consequently, the resulted relative link weights are more robust to combat various adverse scenarios such as large viewpoint variations and indiscriminative feature descriptors. Based on the relative link weights generated at each assumed scale change factor, the strongly-associated subgraph can be extracted from the digraph by applying the non-cooperative game theory for handling non-symmetric adjacency matrix issue. All the vertices (i.e., point-to-point correspondences) belonging to the strongly-associated subgraph extracted from the diagraph established at an assumed scale change factor are collectively treated as one common visual pattern; hopefully, this set of vertices corresponds to one visual object. If this is not the case, our proposed topological splitting algorithm might be able to further discriminate them. Extensive experiments have been conducted on the simulated SIFT feature points for standing out the technical challenges, followed by performing evaluations on six thoughtfully chosen natural image pairs and Columbia dataset to demonstrate the efficacy and robustness of the proposed method. For the third contribution, feature contrast is first introduced as a measurement of the degree of self-similarity contained in an image pair. Note that, for an image pair with strong self-similarity, the established SIFT feature descriptors would be quite similar to each other, therefore the feature contrast is low. The FHE is then proposed to equalize SIFT feature descriptors by independently modifying the vector-component values of feature descriptors at each vector dimension; consequently, the feature contrast is effectively enhanced for the purpose of better discrimination of the feature descriptors. Extensive simulation results have clearly shown that our proposed FHE method could effectively improve the precision of SIFT-based point-to-point correspondences, especially to those image pairs containing a large amount of self-similar regions. As expected, if the image pairs contain only a few or even no self-similar regions, the performance gain would be marginal in this case.