Efficient Layered Parallel Architecture and Application for Large Matrix LDPC Decoder

This paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. This architecture exploits the iterative decomposition of check-node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. The proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of $10 -^{6}$ between 2 to 4 dB of bit-energy to noise-power-spectral-density $(\mathrm{E}_{b}/ \mathrm{N}_{0})$ with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. The VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).

Modern cellular systems rely on high-capacity and low-latency optical networks to meet ever-increasing data demands. Centralized Radio Access Network (C-RAN) architectures offer a cost-effective approach for deploying mobile infrastructures. In this work, we propose a flexible and cost-efficient fronthaul topology that combines Wavelength Division Multiplexing (WDM) passive optical networks (PONs) with free-space optical (FSO) links. To enhance overall system performance, we introduce Low-Density Parity Check (LDPC) decoding, which provides robust error-correction capabilities against atmospheric turbulence and noise. Our system transmits 20 Gbps, 16-QAM intensity-modulated orthogonal frequency-division multiplexing (OFDM) signals, achieving a substantial reduction in bit error rate (BER). Numerical results show that the proposed WDM-PON-FSO architecture, augmented with LDPC decoding, maintains reliable transmission over 2 km under strong turbulence conditions.

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

Low Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means its actual building exists that enables outer edge to be closely intended for symmetry of a channel with no memory. FPGA or Field Programmable Gate Array is based on configurable logic block (CLB) and is a semiconductor gadget that is associated by virtue of programmable interconnects. FPGAs are highly robust and can be created or designed as per the application or usefulness prerequisite of application. This research paper presents adaptable and more compatible LDPC decoder in change for other general LDPC decoder. This decoder has a completely adaptable LDPC plan in FPGA, which supports distinct codes and rate of information. The design is implemented in Xilinx ISE 14.2 software using VHDL programming and synthesized on SPARTAN 3E FPGA. Keywords: Sparse bipartite graph, threshold, Shannon limit, Very High Speed Integrated Circuit Hardware Description Language (VHDL) Cite this Article Sachit Gupta, Richa, Adesh Kumar. FPGA Implementation of LDPC Codes. Journal of Telecommunication, Switching Systems and Networks . 2018; 5(1): 21–28p.

The joint Viterbi detector/decoder (JVDD) has been proposed as an alternative to the powerful and ubiquitous low-density parity check (LDPC) coding schemes, that are used in the majority of channel coding applications today. At shorter block lengths, the JVDD is able to outperform the state-of-the-art LDPC decoder that can be found in many of today’s systems, from deep-space communications to the digital video broadcasting standard, to the advanced television standard committee 3.0. Researchers have developed the tools to analyze the performance of the LDPC decoder, which is known as the sum-product algorithm or message passing algorithm. These tools include density evolution (DE) and extrinsic information transfer (EXIT) charts. To date, no similar such analysis exists for the JVDD. In the current paper we perform a similar preliminary analysis on the JVDD algorithm akin to what DE and EXIT charts are for the LDPC decoder. The current new analysis of the JVDD allows prediction of its probability of error based on the probability distribution functions of the metrics used within the algorithm. Our analysis plays a similar role to the abovementioned tools developed for the LDPC decoder: it allows us to predict the performance of the JVDD under various conditions (such as varying SNR’s, thresholds, and block lengths), it improves our understanding of the JVDD algorithm and the match against Monte-Carlo simulations verifies our assumptions on the main error-causing mechanisms within the JVDD.

The written-in errors in bit patterned media recording (BPMR) system cause the erroneous bits during the writing process leading to the performance degradation. In this work, we propose the pattern-dependent modified log-likelihood ratio (LLR) usage in low-density parity check (LDPC) decoder to reduce the written-in errors and also improve the write margin. Unlike the existing works, LLR computed based on the input data patterns is used at the LDPC decoder for the cascaded written-in error channel (WEC) with the additive white Gaussian noise (AWGN) channel. The proposed LDPC decoder outperforms the one with conventional LLR in terms of both the write margin, when the SNR is fixed at 5.5 dB, and the performance of LDPC decoder. The SNR gain is about 0.2 dB at the BER of 10- 6.

In this letter, we present design and implementation of a parallel software low-density parity-check (LDPC) decoding algorithm on graphics processing units (GPUs). As a solution for the LDPC decoder, dedicated application-specific integrated circuit or field programmable gate array implementations is proposed in recent years in order to support high throughput despite their long deployment cycle, high design, and especially fixed functionalities. On the other hand, the implementations on GPU as a software solution provide flexible, scalable, and less expensive solutions in a shorter deployment cycle. We present some GPU-based optimizations for a major LDPC decoder algorithm to obtain high throughput in digital communication systems. Experimental results demonstrate that the proposed LDPC decoder achieves more than 1.27 Gb/s peak throughput on a single GPU.

Scheduling strategy is considered an important aspect of belief-propagation (BP) decoding of low-density parity-check (LDPC) codes because it affects the decoder's convergence rate, decoding complexity and error-correction performance. In this paper, we propose two new scheduling strategies for the BP decoding of non-binary LDPC (NB-LDPC) codes. Both the strategies are devised based on the concept of check node reliability and employ a heuristically defined threshold which can adapt to the communication channel variations. As the scheduling strategies only update a subset of the check nodes in each iteration, they result in reduced iteration cost. Furthermore, since the BP performs suboptimally for finite-length LDPC codes, especially for short-length LDPC codes, by enhancing the message propagation over the Tanner Graphs of short-length NB-LDPC codes, the new scheduling strategies can even improve the error-correction performances of BP decoding. Simulation results demonstrate that the new scheduling strategies provide good performance/complexity tradeoffs.

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.

Low-density parity check (LDPC) codes can achieve performances close to the Shannon limit and they have been widely adopted for various communication standards. However, the irregular message exchange pattern of LDPC codes is a major challenge for decoder design. Additionally, there is a great demand for integrating diverse applications onto a single system where a flexible, scalable and efficient implementation of LDPC decoding is highly preferable. With the enormous computing power provided by integrating many processors on a single chip in advanced process technology, a multiprocessor platform is regarded as a promising solution to tackle these design challenges. In this work, we devised a parallelisation scheme to implement LDPC decoding on a multiprocessor platform. By using a distributed and cooperative way for LDPC decoding, the memory bottleneck, commonly seen in LDPC decoder design, is eliminated. Moreover, we used a graph spectra-based mapping algorithm to reduce heavy message exchanges among processors during the decoding process. Compared to the sequential mapping strategy, our approach has successfully decreased the amount of inter-processor communication by up to 48%/45%/40% for 16/32/64-processor platforms, respectively. Cycle-accurate simulation results from various LDPC codes demonstrate that desirable scalability and speedups are obtained by our approach.

Parallel decoding is required for low density parity check (LDPC) codes to achieve high decoding throughput, but it suffers from a large set of registers and complex interconnections due to randomly located 1's in the sparse parity check matrix. This paper proposes a new LDPC decoding architecture to reduce registers and alleviate complex interconnections. To reduce the number of messages to be exchanged among processing units, two data flows that can be loosely coupled are developed by allowing duplicated operations. In addition, a partially parallel architecture is proposed to promote the memory usage and an efficient algorithm that schedules the processing order of the partially parallel architecture is also proposed to reduce the overall processing time by overlapping operations. To verify the proposed architecture, a 1024 bit rate-1/2 LDPC decoder is designed using a 0.18 /spl mu/m CMOS process. The decoder occupies an area of 10.08mm/sup 2/ and provides almost 1Gbps decoding throughput at the frequency of 200MHz.

This paper investigates the detection schemes for single-carrier underwater acoustic communications over the severe time-dispersive channels. A low-density parity-check (LDPC) code is employed for the improvement of the equalization performance. A detection scheme with Turbo conception is proposed which includes a LDPC decoder in the feedback loop of an iterative block decision feedback equalizer (IB-DFE), combining the iterative frequency domain equalization of IB-DFE with the iterative LDPC decoding. The external messages are fully exchanged between the IB-DFE and the decoder during the processing of the joint iterative equalization and decoding. The numerical results demonstrate that the decision signals with higher reliability from the LDPC decoder accelerate the convergence of the equalizer and enhance the detection performance, yielding up to 6 dB performance gains when compared with the scheme without LDPC code. Compared with the concatenated scheme in which the process of the iterative frequency domain equalization is serial concatenated with that of the iterative LDPC decoding, the combined scheme obtains about 2 dB performance gains.

Analog computation is potentially more efficient in certain arithmetic operations since a single wire can represent multiple bits of information, while digital systems retain advantages, for example, in logical operations. However, the use of conventional voltage-domain analog computation [1, 2] is limited due to its poor scalability, design complexity, and the overhead of interface circuits (i.e. ADC/DAC) to a surrounding digital system. Therefore, an alternate technique is required for exploiting the efficiency of analog computation. In this paper, we propose time-domain analog and digital mixed (TDMixed) signal processing, wherein time instead of voltage is utilized as the analog signal. To verify the validity of the TDMixed signal processing, we implement an (32, 8) low-density parity-check (LDPC) decoder in 65nm CMOS. The decoder achieves power and area efficiencies of 10.4pJ/b and 6.1Gb/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

In this paper, we propose an efficient controller design of barrel shifter for reconfigurable low-density parity-check (LDPC) decoders, which leads to significant reduction in hardware complexity. Since the structured LDPC codes for the most modern wireless communication systems include multiple code rates, various block lengths, and different sizes of submatrices, a reconfigurable LDPC decoder is desirable and the barrel shifter needs to be programmable. Even though the Benes network can be optimized for the barrel shifting networks of reconfigurable LDPC decoder, it is not trivial to generate all the control signals for numerous 2times2 switches on-the-fly. A novel simplified algorithm capable of generating all the control signals is proposed using the properties that both the full-size Benes network can be broken into two half-size Benes networks and the barrel shifters needed in the structured LDPC decoders require only cyclic shifts. The proposed algorithm can be easily implemented with a small numbers of gates. Compared with the direct implementation using a dedicated look-up table, the proposed algorithm achieves a significant hardware reduction in implementing a reconfigurable LDPC decoder.

$A$ scheduling scheme for multi-core Low-Density Parity-Check (LDPC) decoding is proposed to make full use of logical resources and to maximize the decoding throughput in the high-speed communication systems. In the proposed scheme, consecutive code blocks are processed in different decoding cores according to a variable allocation sequence which is decided by the parity checking result of the decoding sequence. And the scheme is mathematically analyzed with the Gaussian approximation analyzing algorithm and the Sum-Product Algorithm (SPA). It is shown that the proposed scheme can improve the decoding throughput by up to 130% compared to the conventional multicore parallel architectures.