GPU-Based Gigabit LDPC Decoder

Previous studies that used Graphics Processing Units (GPUs) to decode Low Density Parity Check (LDPC) codes for DVB-S2 employed inter-codeword parallelism and/or Turbo Decoding Message Passing (TDMP) to achieve high throughput. By converting the LDPC parity check matrix into a quasi-cyclic structure, we show that LDPC encoding can be efficiently implemented on a GPU, and a different approach to LDPC decoding with intra-codeword parallelism and early termination that can achieve approximately 100 Mbps increase in throughput per 0.1 dB increase in signal-to-noise ratio and, for some cases, achieve 1 Gbps or greater overall throughput.

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

This paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. This architecture exploits the iterative decomposition of check-node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. The proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of $10 -^{6}$ between 2 to 4 dB of bit-energy to noise-power-spectral-density $(\mathrm{E}_{b}/ \mathrm{N}_{0})$ with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. The VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).

Low-Density Parity-Check (LDPC) codes are powerful error correcting codes. LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years. This paper describes two strategies to parallelize min-sum decoding of irregular LDPC codes. The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture (CUDA) to parallelize LDPC decoding on Graphics Processing Units (GPUs). Empirical studies on data with various scales show that the performance of these decoding processes is improved by these parallel strategies and the GPUs provide more efficient, fast implementation decoder.

For a 50G passive optical network (PON) low-density parity-check (LDPC) decoder, decoding performance and area efficiency must be balanced. This paper adopts a layered decoder method to improve the area efficiency of the decoder. By parallel processing of three submatrices and storage reuse of node information, optimizing the matrix partitioning and processing order of the 50G-PON standard, the throughput of 1235 bps was reached under 100 MHz circuit frequency in field-programmable gate array (FPGA) implementation, and 9.864 Gbps was achieved based on Taiwan semiconductor manufacturing company (TSMC) 65 nm synthesis with 800 MHz circuit frequency in an area of 2.61 mm2 by proposing a mechanism of spare decision storage to avoid errors caused by quantization overflow of the decoder and using full verification to terminate decoding in advance to improve performance. Finally, at an input bit error rate (BER) of 2.3×10−2 (signal-to-noise ratio (SNR) of about 3.72 dB), the output BER was lower than 10−12, and the throughput area rate (TAR) also increased by 2 to 4 times compared with other papers. In conclusion, an area-efficient LDPC decoder without sacrificing decoding performance is made.

$A$ scheduling scheme for multi-core Low-Density Parity-Check (LDPC) decoding is proposed to make full use of logical resources and to maximize the decoding throughput in the high-speed communication systems. In the proposed scheme, consecutive code blocks are processed in different decoding cores according to a variable allocation sequence which is decided by the parity checking result of the decoding sequence. And the scheme is mathematically analyzed with the Gaussian approximation analyzing algorithm and the Sum-Product Algorithm (SPA). It is shown that the proposed scheme can improve the decoding throughput by up to 130% compared to the conventional multicore parallel architectures.

This paper presents a parallel system capable of accelerating biological sequence alignment on the graphics processing unit (GPU) grid. The GPU grid in this paper is a desktop grid system that utilizes idle GPUs and CPUs in the office and home. Our parallel implementation employs a master-worker paradigm to accelerate an OpenGL-based algorithm that runs on a single GPU. We integrate this implementation into a screensaver-based grid system that detects idle resources on which the alignment code can run. We also show some experimental results comparing our implementation with three different implementations running on a single GPU, a single CPU, or multiple CPUs. As a result, we find that a single non-dedicated GPU can provide us almost the same throughput as two dedicated CPUs in our laboratory environment, where GPU-equipped machines are ordinarily used to develop GPU applications. In a dedicated environment, the GPU-accelerated code achieves five times higher throughput than the CPU-based code. Furthermore, a linear speedup of 30.7X is observed on a 32-node cluster of dedicated GPUs. We also implement a compute unified device architecture (CUDA) based algorithm to demonstrate further acceleration.

In high density patterned media storage system, the “multiple islands per read head” model is taken into account for inter-track interference (ITI) in bit-patterned media (BPM). It has been proposed that low-density parity-check (LDPC) codes could improve the symbol error rate (SER) performance significantly when only considering AWGN noise alone over the storage channel. LDPC decoding algorithm could be applied in LDPC joint decoder of patterned media storage system. In this paper, we proposed a decoding algorithm of serial belief propagation (SBP) with a stop updating criterion for LDPC decoder. Simulation results show that the proposed decoding algorithm could reduce the times of generating and propagating the message in decoding with negligible error rate performance loss over AWGN channels when appropriately choosing the parameter that determines which variable node has been converged. By taking advantage of extrinsic information transfer (EXIT) charts, it is demonstrated that the proposed decoding algorithm could maintain superior SER performance and convergence rate compared with the traditional SBP decoding algorithm. To further explore the performance of the proposed decoding algorithm in “multiple islands per read head” model, we performed a large number of simulations over this channel model with different distribution percentages between the AWGN and the island position jitter noise. Simulation results show that the LDPC codes could improve the SER performance when considering jitter noise while the proposed decoding algorithm behaves excellently over the patterned media storage channel and over the AWGN channel.

Scheduling strategy is considered an important aspect of belief-propagation (BP) decoding of low-density parity-check (LDPC) codes because it affects the decoder's convergence rate, decoding complexity and error-correction performance. In this paper, we propose two new scheduling strategies for the BP decoding of non-binary LDPC (NB-LDPC) codes. Both the strategies are devised based on the concept of check node reliability and employ a heuristically defined threshold which can adapt to the communication channel variations. As the scheduling strategies only update a subset of the check nodes in each iteration, they result in reduced iteration cost. Furthermore, since the BP performs suboptimally for finite-length LDPC codes, especially for short-length LDPC codes, by enhancing the message propagation over the Tanner Graphs of short-length NB-LDPC codes, the new scheduling strategies can even improve the error-correction performances of BP decoding. Simulation results demonstrate that the new scheduling strategies provide good performance/complexity tradeoffs.

Modern cellular systems rely on high-capacity and low-latency optical networks to meet ever-increasing data demands. Centralized Radio Access Network (C-RAN) architectures offer a cost-effective approach for deploying mobile infrastructures. In this work, we propose a flexible and cost-efficient fronthaul topology that combines Wavelength Division Multiplexing (WDM) passive optical networks (PONs) with free-space optical (FSO) links. To enhance overall system performance, we introduce Low-Density Parity Check (LDPC) decoding, which provides robust error-correction capabilities against atmospheric turbulence and noise. Our system transmits 20 Gbps, 16-QAM intensity-modulated orthogonal frequency-division multiplexing (OFDM) signals, achieving a substantial reduction in bit error rate (BER). Numerical results show that the proposed WDM-PON-FSO architecture, augmented with LDPC decoding, maintains reliable transmission over 2 km under strong turbulence conditions.

Low-density parity check (LDPC) codes can achieve performances close to the Shannon limit and they have been widely adopted for various communication standards. However, the irregular message exchange pattern of LDPC codes is a major challenge for decoder design. Additionally, there is a great demand for integrating diverse applications onto a single system where a flexible, scalable and efficient implementation of LDPC decoding is highly preferable. With the enormous computing power provided by integrating many processors on a single chip in advanced process technology, a multiprocessor platform is regarded as a promising solution to tackle these design challenges. In this work, we devised a parallelisation scheme to implement LDPC decoding on a multiprocessor platform. By using a distributed and cooperative way for LDPC decoding, the memory bottleneck, commonly seen in LDPC decoder design, is eliminated. Moreover, we used a graph spectra-based mapping algorithm to reduce heavy message exchanges among processors during the decoding process. Compared to the sequential mapping strategy, our approach has successfully decreased the amount of inter-processor communication by up to 48%/45%/40% for 16/32/64-processor platforms, respectively. Cycle-accurate simulation results from various LDPC codes demonstrate that desirable scalability and speedups are obtained by our approach.

In this paper, we investigate the soft iterative decoding technique for ternary recoding systems with run-length-limited (RLL) constraints. We employ a simple binary-to-ternary RLL encoder following the LDPC (low density parity check) encoder. In the decoder, the iteratively passing of soft information between the LDPC decoder and a detector is used, where the detector is constructed for a combination of the RLL encoder, PLM (pulse length modulation) precoder and the partial response channel. We provide two different decoding algorithms. For one of the decoding algorithm, we are able to obtain bit-error-rate performance which is inferior to the comparable system without considering the RLL constraint for the high sign-to-noise ratio (SNR) regime and is better for the low-to-moderate SNR regime.

This paper investigates the detection schemes for single-carrier underwater acoustic communications over the severe time-dispersive channels. A low-density parity-check (LDPC) code is employed for the improvement of the equalization performance. A detection scheme with Turbo conception is proposed which includes a LDPC decoder in the feedback loop of an iterative block decision feedback equalizer (IB-DFE), combining the iterative frequency domain equalization of IB-DFE with the iterative LDPC decoding. The external messages are fully exchanged between the IB-DFE and the decoder during the processing of the joint iterative equalization and decoding. The numerical results demonstrate that the decision signals with higher reliability from the LDPC decoder accelerate the convergence of the equalizer and enhance the detection performance, yielding up to 6 dB performance gains when compared with the scheme without LDPC code. Compared with the concatenated scheme in which the process of the iterative frequency domain equalization is serial concatenated with that of the iterative LDPC decoding, the combined scheme obtains about 2 dB performance gains.

Low-density parity-check (LDPC) codes are widely used in many radio systems due to its superior performance and Software Defined Radio (SDR) is an emerging paradigm of the wireless communication system design due to its good flexibility and adaptability. However, LDPC decoding is computationally intensive and the implementation of it on software in a parallel way is quite challenging due to the characteristics of LDPC decoding and structures of software. In this paper, we presented an efficient software implementation of the LDPC decoder using the Parallel Code Block Decoding mode for the WiMAX SDR base band system on IBM CELL Broadband Engine (BE). With a single Synergistic Processor Element (SPE) running at 3.2GHz, the implemented LDPC decoder can achieve a throughput up to 1.71 Mbps. With eight SPEs working in parallel, the decoder can obtain the throughput more than 13Mbps, which can meet the WiMAX system requirement at 5MHz bandwidth mode.

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.