Efficient methods for embedded system design space exploration

ERDSE: efficient reinforcement learning based design space exploration method for CNN accelerator on resource limited platform

A large body of work can be found in literature on Design Space Exploration (DSE) methods for distributed embedded system architecting (DESA). However, almost none of these methods is successfully adopted in automotive industry. To clarify the reasons, this paper 1) analyzes the current state of the art (SOTA) on DSE methods for DESA through a systematic literature study, focusing on the assumed architecting process and concerns; 2) investigates the state of practice (SOP) on DESA in the automotive industry through a literature study and interviews with experienced system architects from five different automotive manufacturers; and 3) analyzes the gap between SOTA and SOP, and thereby discusses potential improvements of DSE methods.

Industrial Cyber-Physical Systems (CPS) are com-plex heterogeneous and distributed computing systems, typically integrating and interconnecting a large number of subsystems and containing a substantial number of hardware and software components. Producers of these distributed Cyber-Physical Systems (dCPS) face serious challenges with respect to designing the next generations of these machines and require proper support in making (early) design decisions to avoid expensive and time consuming oversights. This calls for efficient and scalable system-level Design Space Exploration (DSE) methods for dCPS. In this position paper, we review the current state of the art in DSE, and argue that efficient and scalable DSE technology for dCPS is more or less non-existing and constitutes a largely unchartered research area. Moreover, we identify several re-search challenges that need to be addressed and discuss possible directions for targeting such DSE technolozy for dCPS.

Convolutional Neural Network (CNN) models for modern applications are becoming increasingly deep and complex. Thus, the number of different CNN mapping possibilities when deploying a CNN model on multiple edge devices is vast. Design Space Exploration (DSE) methods are therefore essential to find a set of optimal CNN mappings subject to one or more design requirements. In this paper, we present an efficient DSE methodology to find (near-)optimal CNN mappings for distributed inference at the edge. To deal with the vast design space of different CNN mappings, we accelerate the searching process by proposing and utilizing a multi-stage hierarchical DSE approach together with a tailored Genetic Algorithm as the underlying search engine.

The advent of additive manufacturing (AM) brings many benefits in terms of lightweight design. However, there is no established design for additive manufacturing (DfAM) method available, nor are all the impacts and constraints on the product and development process known. Therefore, a method to redesign existing products for AM is proposed. It consists of functional decomposition enhanced by constraints identification, and analyses of the impact on the design space. Furthermore, the approach defines a coupling of function and geometry models to support an inter-domain redesign process. The approach has been successfully applied in an industrial collaboration project with three aerospace companies, where the support of the method for design space exploration has been recognised. Future work sees the use of this method for design space exploration even outside the AM domain, but a more methodical definition of the relationship between the functional and geometrical domain is required to do so.

Background: The mobility domains are moving towards the adoption of multicore technology. Appropriate methods, techniques, and tools need to be developed or adapted in order to fulfill the existing requirements. This is a case for design space exploration methods and tools. Objective: Our goal was to understand the importance of different design space exploration goals with respect to their relevance, frequency of use, and tool support required in the development of multicore systems from the point of view of the ARAMiS project members. Our aim was to use the results to guide further work in the project. Method: We conducted a survey regarding the current state of the art in design space exploration in industry and research and collected the expectations of project members regarding design space exploration goals. Results: The results show that design space exploration is an important topic in industry as well as in research. It is used very often with different important goals to optimize the system. Conclusions: Current tools provide only partial solutions for design space exploration. Our results can be used for improving them and guiding their development according to the priorities explained in this contribution.

Customized accelerators for Convolutional Neural Network (CNN) can achieve better energy efficiency than general computing platforms. However, the design of a high-performance accelerator should take into account a variety of parameters and physical constraints. The increasing parameters and tighter constraints gradually complicate the design space, which poses new challenges to the capacity and efficiency of design space exploration methods. In this paper, we provide a novel design space exploration method named ACDSE for optimizing the design process of CNN accelerators. ACDSE implements the adaptive compression mechanism to dynamically adjust the search range and prune low-value design points according to the exploration states. As a result, it can focus on valuable subspace while also improving exploration capacity and efficiency. Additionally, we implement ACDSE to address the problem of CNN accelerator latency optimization. The experiment indicates that, compared to former DSE methods, ACDSE can reduce latency and increase efficiency by 1.39x-5.07x and 2.07x-43.87x, respectively, under the most stringent constraint conditions, demonstrating its superior adaptability to the complicated design space.

Nowadays, integration of a large number of processors on the same silicon die has become technically possible; however these multiprocessor system-on-chips (MPSoC) require new design methodologies, and therefore design space exploration (DSE) methods should be utilized. Also, these new methods should deal with problems like deep submicron effects and design complexities on one hand, and meet the time-to-market requirements on the other hand; hence they usually experience a tradeoff between precision of results and the exploration time. In this paper, we present a statistical application model in order to speed up the MPSoC design space exploration process. We also introduce our exploration tool, developed based on this model, and present the simulation results to prove its correctness.

Designing next generation distributed CyberPhysical Systems (dCPS) requires effective Design Space Exploration (DSE) methods to evaluate system design alternatives and their impact on performance. While existing DSE approaches focus on hardware optimization and software-to-hardware mapping, they often overlook parallel execution opportunities within software tasks. Current application workload models for complex dCPS assume fixed execution orders, limiting the ability to explore and exploit software parallelism. To address this issue, we propose refined workload models derived from execution traces that capture both inter- and intra-process dependencies. Building on these models, we present a method to identify tasks that can be safely reordered or executed in parallel without modifying the existing software implementation. We validate our approach through a case study on the ASML Twinscan lithography machine, demonstrating measurable performance improvements without impacting the system functional correctness.

Coarse-grained reconfigurable cryptographic logic arrays (CGRCAs) have become an important platform for hardware implementation of cryptographic algorithms due to their good balance between performance and flexibility. However, existing CGRCA architectures suffer from low hardware resource utilization and low performance of cryptographic algorithms with chained operation modes (e.g., CBC mode of block cipher algorithms). In this paper, an efficient design method for highperformance and high-resource-utilization CGRCA is proposed. The structural characteristics, data dependencies, and parallelism of symmetric cryptographic algorithms are analyzed to determine the core design requirements of the CGRCA. Moreover, multi-task interleaved pipelining (MTIP) and virtual-path parallel processing (VPP) techniques are adapted to improve the parallel processing capability of the CGRCA. On this basis, a chord-based CGRCA architectural model is built to guide the hardware structure design of the CGRCA architecture. Finally, a Bayesian-based design space exploration (DSE) method is proposed to accurately and efficiently determine the core design parameters of CGRCA. The experimental results show that the CGRCA architecture based on the proposed design method can significantly improve performance and hardware resource utilization compared with the traditional CGRCA architectures.

Automatic design space exploration (DSE) tools have been employed over years to evaluate high-performance computer architectures and software designs via on simulation tools. As today's smartphones and consumer electronic devices have become so complex, DSE tools are needed to speed up the design process and produce better designs for the targeted applications. However, traditional simulation tools are too slow to report good system designs in a timely fashion. Thus, in this paper, we propose a framework, called Android Design Space Exploration Tool (ADSET), to facilitate DSE for modern consumer electronic devices. To shorten the exploration time, we adopt a fast full-system modeling technique in our previous work and further develop a parallel DSE method to concurrently evaluate the multiple design points. In our case study, we show that ADSET is capable of modeling Android smartphones in the market and rapidly finds good designs in a large design space.

The development of digital designs today is much more complex than before, as they now impose more severe demands and require greater number of functionalities to be conceived. The current approach, based on the register transfer level (RTL) design methods, can result in extremely long simulation time compounded with time-consuming verification process. Hence, today digital system design begins with modelling at a higher level of design abstraction, that is, the electronic system level (ESL). This paper presents a hardware-software (HW/SW) co-simulation environment based on SystemC for application in the design of system-on-chip (SoC). We discuss the SystemC modelling of the hardware and the software parts of the system, and the interprocess communication module of the co-simulation platform. Its objective is to help designers obtain an appropriate HW/SW partitioning that satisfy specified area-speed design tradeoffs. Besides, an early system verification can also be carried out with a high simulation speed. A case study of a SoC implementing elliptic curve cryptography (ECC) is presented to validate the co-simulation platform in terms of system functionality verification and design space exploration.

In this paper, we present a hardware sharing method for design space exploration of multiprocessor embedded systems. In our prior work, we had developed a system-level design tool which automatically synthesizes communications among the processes. In this work, we have extended our tool so that the tool can automatically synthesize communications which realize sharing of hardware among different processes. With the tool, designers only need to change the mapping information for hardware sharing. Designers therefore can easily explore wider design space with hardware sharing. A case study shows the effectiveness of our hardware sharing method.

Multidisciplinary preliminary engine design involves a large number of tools and participants. The highly iterative and multidisciplinary workflows make it difficult to evaluate the influence of individual design parameters on the final result.
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\nWith high-dimensional parameter studies the design space of the system can be investigated. However, the evaluation of the results can rapidly become very challenging. The screening method of elementary effects according to Morris as a method of global sensitivity analysis (GSA) can provide useful insights from even a small number of evaluations. Especially a reduction of the dimensionality due to factor fixing of input parameters with low influence on the problem and factor prioritization of important parameters are addressed by GSA. The purpose of the paper is to demonstrate the application of the method by means of a coupled process which includes performance calculations of the entire engine system and preliminary design of a high-pressure compressor. The variation of input parameters of the different disciplines will be investigated and it will be shown that the Morris screening characteristics allow the evaluation of parameters within the design space in particular with regard to a classification of the significance for the result variables. This shows in the application example that in the comparison parameters with a clear influence emerge from both disciplines.

Processors that deploy fine-grained reconfigurable fabrics to implement application-specific accelerators on-demand obtained significant attention within the last decade. They trade-off the flexibility of general-purpose processors with the performance of application-specific circuits without tailoring the processor towards a specific application domain like Application Specific Instruction Set Processors (ASIPs). Vast amounts of reconfigurable processors have been proposed, differing in multifarious architectural decisions. However, it has always been an open question, which of the proposed concepts is more efficient in certain application and/or parameter scenarios. Various reconfigurable processors were investigated in certain scenarios, but never before a systematic design space exploration across diverse reconfigurable processor concepts has been conducted with the aim to aid a designer of a reconfigurable processor. We have developed a first-of-its-kind comprehensive design space exploration tool that allows to systematically explore diverse reconfigurable processors and architectural parameters. Our tool allows presenting the first cross-architectural design space exploration of multiple fine-grained reconfigurable processors on a fair comparable basis. After categorizing fine-grained reconfigurable processors and their relevant parameters, we present our tool and an in-depth analysis of reconfigurable processors within different relevant scenarios.