Unraveling Parallelism in Automated Workload Modeling for Distributed Cyber-Physical Systems

ERDSE: efficient reinforcement learning based design space exploration method for CNN accelerator on resource limited platform

A large body of work can be found in literature on Design Space Exploration (DSE) methods for distributed embedded system architecting (DESA). However, almost none of these methods is successfully adopted in automotive industry. To clarify the reasons, this paper 1) analyzes the current state of the art (SOTA) on DSE methods for DESA through a systematic literature study, focusing on the assumed architecting process and concerns; 2) investigates the state of practice (SOP) on DESA in the automotive industry through a literature study and interviews with experienced system architects from five different automotive manufacturers; and 3) analyzes the gap between SOTA and SOP, and thereby discusses potential improvements of DSE methods.

Industrial Cyber-Physical Systems (CPS) are com-plex heterogeneous and distributed computing systems, typically integrating and interconnecting a large number of subsystems and containing a substantial number of hardware and software components. Producers of these distributed Cyber-Physical Systems (dCPS) face serious challenges with respect to designing the next generations of these machines and require proper support in making (early) design decisions to avoid expensive and time consuming oversights. This calls for efficient and scalable system-level Design Space Exploration (DSE) methods for dCPS. In this position paper, we review the current state of the art in DSE, and argue that efficient and scalable DSE technology for dCPS is more or less non-existing and constitutes a largely unchartered research area. Moreover, we identify several re-search challenges that need to be addressed and discuss possible directions for targeting such DSE technolozy for dCPS.

Convolutional Neural Network (CNN) models for modern applications are becoming increasingly deep and complex. Thus, the number of different CNN mapping possibilities when deploying a CNN model on multiple edge devices is vast. Design Space Exploration (DSE) methods are therefore essential to find a set of optimal CNN mappings subject to one or more design requirements. In this paper, we present an efficient DSE methodology to find (near-)optimal CNN mappings for distributed inference at the edge. To deal with the vast design space of different CNN mappings, we accelerate the searching process by proposing and utilizing a multi-stage hierarchical DSE approach together with a tailored Genetic Algorithm as the underlying search engine.

Nowadays, integration of a large number of processors on the same silicon die has become technically possible; however these multiprocessor system-on-chips (MPSoC) require new design methodologies, and therefore design space exploration (DSE) methods should be utilized. Also, these new methods should deal with problems like deep submicron effects and design complexities on one hand, and meet the time-to-market requirements on the other hand; hence they usually experience a tradeoff between precision of results and the exploration time. In this paper, we present a statistical application model in order to speed up the MPSoC design space exploration process. We also introduce our exploration tool, developed based on this model, and present the simulation results to prove its correctness.

Coarse-grained reconfigurable cryptographic logic arrays (CGRCAs) have become an important platform for hardware implementation of cryptographic algorithms due to their good balance between performance and flexibility. However, existing CGRCA architectures suffer from low hardware resource utilization and low performance of cryptographic algorithms with chained operation modes (e.g., CBC mode of block cipher algorithms). In this paper, an efficient design method for highperformance and high-resource-utilization CGRCA is proposed. The structural characteristics, data dependencies, and parallelism of symmetric cryptographic algorithms are analyzed to determine the core design requirements of the CGRCA. Moreover, multi-task interleaved pipelining (MTIP) and virtual-path parallel processing (VPP) techniques are adapted to improve the parallel processing capability of the CGRCA. On this basis, a chord-based CGRCA architectural model is built to guide the hardware structure design of the CGRCA architecture. Finally, a Bayesian-based design space exploration (DSE) method is proposed to accurately and efficiently determine the core design parameters of CGRCA. The experimental results show that the CGRCA architecture based on the proposed design method can significantly improve performance and hardware resource utilization compared with the traditional CGRCA architectures.

Background: The mobility domains are moving towards the adoption of multicore technology. Appropriate methods, techniques, and tools need to be developed or adapted in order to fulfill the existing requirements. This is a case for design space exploration methods and tools. Objective: Our goal was to understand the importance of different design space exploration goals with respect to their relevance, frequency of use, and tool support required in the development of multicore systems from the point of view of the ARAMiS project members. Our aim was to use the results to guide further work in the project. Method: We conducted a survey regarding the current state of the art in design space exploration in industry and research and collected the expectations of project members regarding design space exploration goals. Results: The results show that design space exploration is an important topic in industry as well as in research. It is used very often with different important goals to optimize the system. Conclusions: Current tools provide only partial solutions for design space exploration. Our results can be used for improving them and guiding their development according to the priorities explained in this contribution.

Automatic design space exploration (DSE) tools have been employed over years to evaluate high-performance computer architectures and software designs via on simulation tools. As today's smartphones and consumer electronic devices have become so complex, DSE tools are needed to speed up the design process and produce better designs for the targeted applications. However, traditional simulation tools are too slow to report good system designs in a timely fashion. Thus, in this paper, we propose a framework, called Android Design Space Exploration Tool (ADSET), to facilitate DSE for modern consumer electronic devices. To shorten the exploration time, we adopt a fast full-system modeling technique in our previous work and further develop a parallel DSE method to concurrently evaluate the multiple design points. In our case study, we show that ADSET is capable of modeling Android smartphones in the market and rapidly finds good designs in a large design space.

Designing the next‐generation complex distributed cyber‐physical systems (dCPS) poses significant challenges for manufacturing companies, necessitating efficient design space exploration (DSE) techniques to evaluate potential design decisions and their impact on nonfunctional aspects of the systems, such as performance, reliability and energy consumption. This paper introduces CompDSE, a methodology designed to facilitate the DSE of complex dCPS, specifically focusing on the cyber components, that is, the computing subsystems within dCPS. CompDSE defines and utilises abstract models of the application workload, computing hardware platform and workload‐to‐platform mapping of dCPS, automatically derived from runtime trace data, and integrates them into a discrete event simulation environment to explore various design points. We demonstrate the effectiveness of our methodology through a case study on the ASML TWINSCAN lithography machine, a complex industrial dCPS. The results showcase potential performance enhancements achieved by optimising computing subsystems while considering physical constraints. Evaluating each design point takes under a minute, highlighting the CompDSE efficiency and scalability in tackling complex dCPS with large design spaces.

Customized accelerators for Convolutional Neural Network (CNN) can achieve better energy efficiency than general computing platforms. However, the design of a high-performance accelerator should take into account a variety of parameters and physical constraints. The increasing parameters and tighter constraints gradually complicate the design space, which poses new challenges to the capacity and efficiency of design space exploration methods. In this paper, we provide a novel design space exploration method named ACDSE for optimizing the design process of CNN accelerators. ACDSE implements the adaptive compression mechanism to dynamically adjust the search range and prune low-value design points according to the exploration states. As a result, it can focus on valuable subspace while also improving exploration capacity and efficiency. Additionally, we implement ACDSE to address the problem of CNN accelerator latency optimization. The experiment indicates that, compared to former DSE methods, ACDSE can reduce latency and increase efficiency by 1.39x-5.07x and 2.07x-43.87x, respectively, under the most stringent constraint conditions, demonstrating its superior adaptability to the complicated design space.

Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip area. Simulation, in particular trace-driven simulation, is widely used to estimate cache hit rates. However, simulation is too slow to be deployed in design space exploration, especially when there are hundreds of design points and the traces are huge. In this article, we propose a novel analytical approach for design space exploration of instruction caches. Given the program control flow graph (CFG) annotated only with basic block and control flow edge execution counts, we first model the cache states at each point of the CFG in a probabilistic manner. Then, we exploit the structural similarities among related cache configurations to estimate the cache hit rates for multiple cache configurations in one pass. Experimental results indicate that our analysis is 28--2,500 times faster compared to the fastest known cache simulator while maintaining high accuracy (0.2% average error) in estimating cache hit rates for a large set of popular benchmarks. Moreover, compared to a state-of-the-art cache design space exploration technique, our approach achieves 304--8,086 times speedup and saves up to 62% (average 7%) energy for the evaluated benchmarks.

DNA-based data storage emerged in this decade as a promising solution for long data durability, low power consumption, and high density. However, such technology has not yet reached a good maturity level, requiring many investigations to improve the information encoding and decoding processes. Simulations can be key to overcoming the time and the cost burdens of the many experiments imposed by thorough design space explorations. In response to this, we have developed a DNA storage simulator (DNAssim) that allows simulating the different steps in the DNA storage pipeline using a proprietary software infrastructure written in Python/C language. Among the many operations performed by the tool, the edit distance calculation used during clustering operations has been identified as the most computationally intensive task in software, thus calling for hardware acceleration. In this work, we demonstrate the integration in the DNAssim framework of a dedicated FPGA hardware accelerator based on the Xilinx VC707 evaluation kit to boost edit distance calculations by up to 11 times with respect to a pure software approach. This materializes in a clustering simulation latency reduction of up to 5.5 times and paves the way for future scale-out DNA storage simulation platforms.

The advent of additive manufacturing (AM) brings many benefits in terms of lightweight design. However, there is no established design for additive manufacturing (DfAM) method available, nor are all the impacts and constraints on the product and development process known. Therefore, a method to redesign existing products for AM is proposed. It consists of functional decomposition enhanced by constraints identification, and analyses of the impact on the design space. Furthermore, the approach defines a coupling of function and geometry models to support an inter-domain redesign process. The approach has been successfully applied in an industrial collaboration project with three aerospace companies, where the support of the method for design space exploration has been recognised. Future work sees the use of this method for design space exploration even outside the AM domain, but a more methodical definition of the relationship between the functional and geometrical domain is required to do so.

All computing platforms, from mobile to supercomputers, are becoming more and more heterogeneous and massively parallel. While they can provide higher power efficiency and computation throughput, effective and confident use of these systems always requires knowledge about low-level programming. The average time necessary to develop and optimize a design on heterogeneous platforms is higher and higher compared to typical homogeneous systems. Dataflow models of computation (MoC) are quickly becoming the common practice in heterogeneous systems development. In domains such as signal processing and multimedia communication, dataflow MoCs have become accepted as standard. However, the shift from a sequential and architecture-specific MoC to a dataflow MoC still uncovers several programming and development challenges. The Cal Actor Language (CAL) is a recently-specified dataflow and actor-based language capable of concisely expressing complex and general purpose parallel applications. However, design tools supporting this language are generally not adequate to fully exploit its features and expressiveness power. In fact, they generally restrict its MoC in order to reduce the design space exploration (DSE) effort. The objective of this thesis is to provide a DSE methodology where all the features of CAL and dynamic dataflow MoCs can be exploited in a more general and effective manner. This dissertation illustrates a novel profiling, analysis and performance estimation methodology for the DSE of dynamic dataflow programs. The main research contributions of this thesis are: the formalization of a graph-based representation of the program execution called an execution trace graph (ETG); the formalization of a systematic methodology for profiling generic dynamic dataflow programs through their code interpretation; the formalization of a complete DSE methodology for dynamic dataflow programs in order to efficiently identify close-to-optimal design points according to various and tailored performance merit functions. In particular, the following design space optimization problems for dynamic dataflow programs are addressed: the analysis of the hotspots and the algorithmic bottlenecks of a parallel program; the bounding and optimization of the buffer size configuration for complex designs; the dynamic power dissipation minimization of programs implemented in multi-clock domain architecture. Furthermore, theoretical concepts like the design space critical path and the potential speedup of a dataflow application have been defined and revisited, respectively. The thesis also presents a DSE framework developed in order to demonstrate the effectiveness of this design methodology.

Design space exploration is the process of analyzing several functionally equivalent alternatives to determine the most suitable one. The synchronous assumption has made it possible to develop efficient procedures for establishing functional equivalence between different implementations in the domain of synchronous circuits as well as in the domain of synchronous reactive systems. We extend this notion to embedded systems that do not satisfy the synchronous assumption inside their boundaries but only at the interface with the environment Leveraging this property, we developed efficient synchronous equivalence analysis algorithms for embedded systems with loops and architectures with multiple computational units. We demonstrate our method on an ATM switch containing many interacting components.