Efficient Reencoder Architectures for Algebraic Soft-Decision Reed–Solomon Decoding

Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can provide substantial coding gain with polynomial complexity. Among the ASD algorithms with practical multiplicity assignment schemes, the Low-Complexity Chase (LCC) decoding can achieve similar or higher coding gain. Interpolation is a major step in ASD. Since the maximum multiplicity of the interpolation point is only one in LCC, the interpolation over each point has low complexity. However, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</sup> test vectors are involved in the LCC, and the interpolation needs to be carried out on each of them. In order to reduce the computational complexity of the overall interpolation, intermediate results can be stored and shared. Nevertheless, the storage requires large memory, which accounts for a significant portion of the overall hardware requirement of the interpolator. In this paper, we propose a novel interpolation procedure, in which the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</sup> test vectors are mapped to the vertices of a dimension-η hypercube and the vectors mapped to adjacent vertices have only one different entry. In addition, a backward interpolation is proposed to support the traversal from one vertex to its neighbors. Traveling through the entire hypercube, the interpolation over each test vector can be done one after another and the memory requirement is reduced by a factor of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η-1</sup> . Efficient architectures are also developed for the proposed interpolation procedure. With about the same latency and the same number of gates as in prior efforts, our architecture can reduce the memory size to 25% and the number of registers to 57% for a (255, 239) RS code with η = 3. The saving further increases with η.

Reed-Solomon (RS) codes are used as error-correcting codes in numerous digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can achieve substantial coding gain with polynomial complexity. Among practical ASD algorithms, the iterative bit-level generalized minimum distance (BGMD) decoding can achieve similar or higher coding gain with lower complexity. The interpolation is a major step of ASD. The maximum achievable speed of this step is limited by the inherent serial nature of the interpolation algorithm. In this paper, a novel interpolation scheme that is capable of combining multiple interpolation iterations, as well as sharing interpolation results from previous decoding iterations, is developed for the iterative BGMD decoding. In addition, efficient VLSI architectures are proposed to implement the developed scheme. Based on the proposed architectures, an interpolator for a (255, 239) RS code is implemented on field programmable gate array (FPGA) devices. On a Xilinx Virtex-II device, our interpolator can achieve a throughput of 440 Mbps, which is 64% higher than the fastest previous design, with 51% less FPGA resource.

This paper presents a high-speed low-complexity Reed-Solomon (RS) decoder architecture using a novel pipelined recursive modified Euclidean (PrME) algorithm block for very high-speed optical communications. The RS decoder features a low-complexity key equation solver using a PrME algorithm block. The recursive structure enables the novel low-complexity PrME algorithm block to be implemented. Pipelining and parallelizing allow the inputs to be received at very high fiber-optic rates, and outputs to be delivered at correspondingly high rates with minimum delay. This paper presents the key ideas applied to the design of an 80-Gb/s RS decoder architecture, especially that for achieving high throughput and reducing complexity. The 80-Gb/s 16-channel RS decoder has been designed and implemented using 0.13-/spl mu/m CMOS technology in a supply voltage of 1.2 V. The proposed RS decoder has a core gate count of 393 K and operates at a clock rate of 625 MHz.

Reed-Solomon (RS) codes are error-correcting codes used in many of today's communication systems. RS encoding and decoding are typically implemented using dedicated hardware elements used in ADSL modems and digital TV. In this paper we propose using software in lieu of a hardware-based RS de-coder. This is accomplished using the Berlekamp-Massey algorithm, implemented on a programmable DSP. This software-based RS decoder using Berlekamp-Massey is implemented on Motorola's MSC8101 StarCore DSP. In order to evaluate the algorithm we use the following criteria: computation cost; cycle count, critical paths in the decoding scheme, and error location in the codeword. Furthermore, we examine the effect of changing the RS code's k, t parameters and its primitive polynomial in real-time implementation. The Berlekamp-Massey algorithm operates over finite field arithmetic, whose steps, as applied on the StarCore DSP, are discussed in detail and specifically evaluated using the assembly code for the syndrome search. We conclude that the Berlekamp-Massey algorithm, used for RS decoding, should be implemented using long codewords.

This paper presents a high-throughput variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS (255,239) code but also various shortened RS codes. Moreover, the variable-length architecture provides low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-nm CMOS standard cell technology, the proposed variable-length RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-Gbps data rate at clock frequency 300 MHz.

Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurring in the transmission process. Since the decoding process for RS codes is rather computation-extensive, special-purpose hardware structures are often necessary for it to meet the real-time requirements. In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for RS decoding. The architecture is developed based on a time domain algorithm using the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder can process one data block every n clock cycles, i.e., the average decoding rate is one symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency.

This paper describes a 10.7 Gb/s throughput FEC (Forward Error Correction) codec LSI for optical transmission systems. In order to reduce the power consumption and logic size, the FEC codec uses a time-multiplexed Reed-Solomon (RS) decoder, which is shared among 4 RS codewords and processes 5 parallel digits. The time-multiplexed RS decoder requires only 58% of the gates and 75% of the power consumption of the conventional decoder. As a result, the codec achieves a low power consumption of only 3.31 W and a low gate count of only 1.1 Mgates using 0.18 /spl mu/m CMOS technology.

Forward error correction (FEC) is a key capability in modern satellite communications that provide the system designer with the needed flexibility to comply with the different applications' requirements. Reed-Solomon (RS) codes are well known for their ability to optimize between the system power, bandwidth, data rate, and the quality of service. This paper introduces an efficient decoding scheme for decoding the RS codes adhering to the Consultative Committee for Space Data Systems (CCSDS) standards based on Justesen's construction of concatenation. To maintain the standard output size, the proposed scheme first encodes every m - 1 bits using the single-parity-check (SPC) code, while the RS code encodes K SPC codewords into N symbols that are of the same size as CCSDS standard. Decoding on the inner SPC code is based on maximum-likelihood decoding Kaneko algorithm, while for the proposed coding scheme, the reduced test-pattern Chase algorithm is adapted for decoding the outer RS code. The simulation results show the coding gains of 1.4 and 7 dB compared with the algebraic decoding of RS codes over the AWGN and Rayleigh fading channels, respectively. Moreover, the adopted reduced test-pattern Chase algorithm for decoding the RS code achieves an overall complexity reduction of 40% compared with the conventional Chase decoding algorithm.

A very-large-scale integration architecture for Reed-Solomon (RS) decoding is presented that is scalable with respect to the throughput rate. This architecture enables given system specifications to be matched efficiently independent of a particular technology. The scalability is achieved by applying a systematic time-sharing technique. Based on this technique, new regular, multiplexed architectures have been derived for solving the key equation and performing finite field divisions. In addition to the flexibility, this approach leads to a small silicon area in comparison with several decoder implementations published in the past. The efficiency of the proposed architecture results from a fine granular pipeline scheme throughout each of the RS decoder components and a small overhead for the control circuitry. Implementation examples show that due to the pipeline strategy, data rates up to 1.28 Gbit/s are reached in a 0.5 /spl mu/m CMOS technology.

Previously, the authors proposed an inverse-free Berlekamp-Massey (1968, 1969) algorithm to simplify the Reed-Solomon (RS) codes. This modified RS decoding method is the best known technique for finding the error locator polynomial. The inverse-free method is generalized to find both errors and erasures. The basic idea of the new procedure is the replacement of the initial condition of the BM algorithm by the Forney (1965) syndromes. With this improved technique, the complexity of time-domain RS decoders for correcting both errors and erasures is reduced substantially from previous approaches.

In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2 K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The (255,239) RS decoder is implemented by 0.25 /spl mu/m CMOS 1P5M standard cells with gate counts of 32.9 K and area of 2.03 mm/sup 2/. Simulation results show our approach can work successfully at the data rate of 2.5-Gbps and achieve 80% reduction of power dissipation on the average.

This paper presents a high-speed low-complexity three-parallel Reed-Solomon (RS) decoder for 6-Gbps mmWave WPAN systems. Three-parallel processing is used to achieve 6-Gbps data throughput and low hardware complexity. Three-way parallelizing for syndrome computation and error correction allow the inputs to be received at very high data rates and the outputs to be delivered at correspondingly high rates with a minimum delay. The proposed three-parallel RS decoder has been implemented 90 nm CMOS technology optimized for a 1.2 V supply voltage. The implementation result shows that the proposed RS decoder can operates at a clock frequency of 400 MHz and has a data throughput 9.6-Gbps. The proposed three-parallel RS decoder architecture has a much higher data processing rate and low hardware complexity, and also can be adapted in the FEC devices for mmWave WPAN systems with a data rate of 6 Gbps and beyond.

This paper presents a multi-mode Reed-Solomon (RS) decoder with folding architecture which has low cost and low power consumption. The solution can be applied into any application that requires multi-mode RS codes. Implemented by SMIC 0.13 μm 1.2 V CMOS technology, the decoder runs at 440MHz clock rate and has a gate count of 65K and die size of 1.18×1.18 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption is 0.25mW per error byte benefiting from the proper mode control, which is quite economical for a multi-mode RS decoder. The maximum error correction capability of the decoder is 32 bytes.

Time domain decoding of extended and doubly extended Reed-Solomon codes are considered for both errors only decoding and errors and erasures decoding. The parity check and generator matrices are given for the singly and doubly extended Reed-Solomon codes in terms of the parity check and generator matrices of the Reed-Solomon codes. Syndrome calculations for the singly and doubly extended codes are discussed and the modifications necessary for the error location and error magnitude calculations are given. The modifications necessary for decoding extended Reed-Solomon codes using the Berlekamp-Massey algorithm and Euclid's algorithm for finding the error magnitudes are presented for both errors only and errors and erasures decoding.

Polar codes are the first provable capacity-achieving channel codes. Despite the splendid performance of long Polar codes, short Polar codes have relatively poor performance compared with other modern channel coding schemes (e.g., Turbo codes and LDPC). In this paper, we explore some practical methods to improve the performance of Polar codes with short to moderate codeword lengths. First, we use Reed Solomon (RS) codes as outer codes. With a specific interleaving strategy, we can concatenate multiple RS codes with one frame of Polar codes. Combining a strategy of allocating unequal RS code rates with the concatenation, different levels of protection are assigned based on the error pattern of successive cancellation list (SCL) decoders. Thus, the finite length performance will certainly be enhanced for this encoding scheme. Meanwhile, the memory size that the original SCL decoding procedure requires is reduced, and the increment of overall decoding complexity is small. Additionally, we propose an intra-frame interleaver to further enhance the performance by dispersing errors. Finally, we designed a list decoding scheme for the proposed multi-RS concatenated Polar codes. Depending on the soft information generated by an SCL decoder, we calculated the reliability of each RS symbol and conducted soft RS decoding. So, the overall performance was enhanced under this joint decoding strategy. Simulation results indicate that the bit error rate (BER) performance of short Polar codes can be well improved.